Process for forming field isolation and a structure over a semiconductor substrate

• US 5,580,815 A
• Filed: 02/22/1994
• Issued: 12/03/1996
• Est. Priority Date: 08/12/1993
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hsu, Ting C., Tobin, Philip J., Parker, Laureen H., Ilderem, Vida, Tseng, Hsing-Huang, Garling, Lisa K., Kolar, David G.
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/200,029
• Time in Patent Office: 1,015 Days
• Field of Search: 437/69, 437/70, 437/72, 437/73
• US Class Current: 438/362
• CPC Class Codes: H01L 21/32 using masks

Abstract

An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.

Claims

1. A process for forming field isolation comprising the steps of:

forming a pad layer over a semiconductor substrate;

depositing an amorphous silicon layer over the pad layer;

incorporating a dopant into the amorphous silicon layer by a manner selected from a group consisting of;

in-situ doping;

furnace doping; and

ion implantation;

annealing the amorphous silicon layer to form an annealed silicon layer;

forming a silicon nitride layer over the pad layer after the step of depositing the amorphous silicon layer;

patterning the silicon nitride layer to form a patterned silicon nitride layer including an opening and a silicon nitride member, wherein the step of patterning is performed after the step of incorporating;

thermally oxidizing the substrate underlying the opening to form a field isolation region within the opening and adjacent to the annealed silicon layer; and

removing the silicon nitride member.

2. The process of claim 1, wherein the step of incorporating is performed such that the amorphous silicon layer includes an n-type dopant and has a doping concentration in a range of 1E17 to 1E20 atoms per cubic centimeter.

3. The process of claim 1, wherein the step of annealing is performed in a furnace at a temperature in a range of about 300-620 degrees Celsius for at least twenty minutes.

4. The process of claim 1, wherein the step of annealing is performed in a rapid thermal processor at a temperature in a range of about 300-800 degrees Celsius for at least five seconds.

5. The process of claim 1, wherein the step of annealing includes a plurality of portions, wherein:

one of the portions is performed in a furnace at a temperature in a range of about 300-620 degrees Celsius; and

another one of the portions is performed in a rapid thermal processor at a temperature in a range of about 300-800 degrees Celsius.

6. The process of claim 1, further comprising a step of forming a first bipolar transistor and a second bipolar transistor after the step of removing the silicon nitride member, wherein the field isolation region lies adjacent to and between the first and second bipolar transistors.

7. A process for forming field isolation comprising the steps of:

forming a pad layer over a semiconductor substrate;

depositing an amorphous silicon layer over the pad layer;

annealing the amorphous silicon layer;

forming a silicon nitride layer over the amorphous silicon layer;

patterning the silicon nitride layer to form a patterned silicon nitride layer including a silicon nitride layer opening and a silicon nitride member;

thermally oxidizing the substrate underlying the silicon nitride layer opening to form a field isolation region within the silicon nitride layer opening; and

removing the silicon nitride member, wherein the annealing step is performed in a separate step from the step of forming the silicon nitride layer and prior to the step of thermally oxidizing the substrate.

8. The process of claim 7, wherein:

the amorphous silicon layer is deposited to a thickness in a range of about 200-700 angstroms;

the silicon nitride layer is formed to a thickness in a range of about 1000-2500 angstroms; and

the pad layer is formed to a thickness no greater than about 40 percent of the thickness of the silicon nitride layer.

9. The process of claim 7, wherein the step of annealing that is performed in a furnace at a temperature in a range of about 300-620 degrees Celsius for at least twenty minutes.

10. The process of claim 7, wherein the step of annealing that is performed in a rapid thermal processor at a temperature in a range of about 300-800 degrees Celsius for at least five seconds.

11. The process of claim 7, wherein the step of annealing is performed at a temperature no higher than 620 degrees Celsius.

12. The process of claim 11, wherein:

the step of annealing is performed after the step of forming the silicon nitride layer; and

the steps of annealing and thermally oxidizing are performed during the same thermal cycle, wherein the annealing step is performed in a separate step from the step of thermally oxidizing the substrate.

13. The process of claim 11, wherein the steps of forming a silicon nitride layer and annealing the amorphous silicon layer are performed during the same thermal cycle.

14. The process of claim 7, wherein the step of annealing the amorphous silicon layer, wherein:

the step of annealing is performed prior to the step of thermally oxidizing;

the step of annealing includes a first portion and a second portion;

the first portion is performed in a furnace at a temperature in a range of about 300-620 degrees Celsius; and

the second portion is performed in a rapid thermal processor at a temperature in a range of about 300-800 degrees Celsius.

15. The process of claim 7, wherein the step of forming the silicon nitride layer is performed at a temperature no greater than 600 degrees Celsius.

16. The process of claim 7, further comprising a step of removing any remaining portion of the amorphous silicon layer after the step of removing the silicon nitride member.

17. The process of claim 7, further comprising a step of forming a first bipolar transistor and a second bipolar transistor after the step of removing the silicon nitride member, wherein the field isolation region lies adjacent to and between the first and second bipolar transistors.

18. A process for forming field isolation comprising the steps of:

forming a pad layer over a semiconductor substrate;

depositing an amorphous silicon layer over the pad layer;

annealing the amorphous silicon layer to form an annealed silicon layer;

forming a silicon nitride layer over the annealed silicon layer before performing a thermal oxidation step;

patterning the silicon nitride layer to form a patterned silicon nitride layer including a silicon nitride layer opening and a silicon nitride member;

thermally oxidizing the substrate underlying the silicon nitride layer opening to form a field isolation region within the silicon nitride layer opening; and

removing the silicon nitride member.

19. The process of claim 18, wherein:

the amorphous silicon layer is deposited to a thickness in a range of about 200-700 angstroms;

the silicon nitride layer is formed to a thickness in a range of about 1000-2500 angstroms; and

the pad layer is formed to a thickness no greater than about 40 percent of the thickness of the silicon nitride layer.

20. The process of claim 18, wherein the step of annealing is performed in a furnace at a temperature in a range of about 300-620 for at least twenty minutes.

21. The process of claim 18, wherein the step of annealing is performed in a rapid thermal processor at a temperature in a range of about 300-800 for at least five seconds.

22. The process of claim 18, wherein the step of annealing is performed in a rapid thermal process at a temperature in a range of about 300-620 for at least thirty seconds.

23. The process of claim 18, wherein the steps of forming and annealing the amorphous silicon layer are performed during the same thermal cycle.

24. The process of claim 18, wherein the steps of annealing the amorphous silicon layer and forming the silicon nitride layer are performed during the same thermal cycle.

25. The process of claim 18, wherein the step of annealing is performed during a thermal cycle separate from both the steps of depositing the amorphous silicon layer and forming the silicon nitride layer.

26. The process of claim 18, wherein the step of annealing includes a first portion and a second portion, wherein:

the first portion is performed in a furnace at a temperature in a range of about 300-620 degrees Celsius; and

the second portion is performed in a rapid thermal processor at a temperature in a range of about 300-800 degrees Celsius.

27. The process of claim 18, wherein the step of annealing is performed using an ambient selected from a group consisting of:

an inert gas;

an inert gas and an oxidizing species, wherein the ambient includes no more than about five volume percent of the oxidizing species;

an inert gas and a chlorinating species, wherein the ambient includes no more than about ten volume percent of the chlorinating species; and

an inert gas, an oxidizing species, and a chlorinating species, wherein the ambient includes no more than about five volume percent of the oxidizing species and no more than about ten volume percent of the chlorinating species.

28. The process of claim 18, further comprising a step of removing any remaining portion of the annealed silicon layer after the step of removing the silicon nitride member.

29. The process of claim 18, further comprising a step of forming a first bipolar transistor and a second bipolar transistor after the step of removing the silicon nitride member, wherein the field isolation region lies adjacent to and between the first and second bipolar transistors.