FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures

• US 5,581,101 A
• Filed: 01/03/1995
• Issued: 12/03/1996
• Est. Priority Date: 01/03/1995
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Wu, Ben S., Ning, Tak H.
• Primary Examiner(s): Fahmy, Wael M.
• Application Number:
  US08/368,069
• Time in Patent Office: 700 Days
• Field of Search: 257/347, 257/350, 257/351, 257/352, 257/524, 257/525
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66265 Thin film bipolar transistors H01L29/66242 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.

Claims

1. A semiconductor structure containing integrated circuits comprising:

a plurality of silicon vertical sidewalls formed as sections of a multisectioned cell, each silicon vertical sidewall being of predetermined thickness and having top, bottom, and substantially vertical front and back silicon surfaces, said silicon sidewalls containing impurity regions of semiconductor devices, said impurity regions being stacked vertically on top of one another in layered planes, each said impurity region contacted electrically at one of said front, back and top surfaces, and wherein said at least one pair of sidewalls having an interconnection between corresponding impurity regions of two semiconductor devices made in a layered plane of said corresponding impurity regions; and

an insulating layer in contact with the bottom surface of said silicon sidewalls; and

an insulating barrier covering said top and vertical front and back surfaces of the silicon sidewall except where electrical contacts to said impurity regions are located.

2. The semiconductor structure of claim 1 wherein at least a pair of sidewalls in a cell have impurity regions of semiconductor devices of the same type, and wherein interconnections are made between the electrical contacts of said impurity regions in a layered plane of the silicon sidewall pair.

3. The semiconductor structure of claim 2 wherein at least a pair of silicon sidewalls forms a pair of complementary semiconductor devices.

4. The semiconductor structure of claim 1 wherein at least a pair of the sidewalls in the cell having impurity regions of semiconductor devices of different type, and wherein at least one interconnection is made between the electrical contacts of said impurity regions in a layered plane of the silicon sidewall pair.

5. The semiconductor structure of claim 4 wherein at least a pair of silicon sidewalls forms a pair of complementary semiconductor devices.