Static discharge circuit having low breakdown voltage bipolar clamp

• US 5,581,104 A
• Filed: 04/18/1995
• Issued: 12/03/1996
• Est. Priority Date: 01/16/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chance, Randal W., Lowrey, Tyler A.
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US08/425,678
• Time in Patent Office: 595 Days
• Field of Search: 357/13, 357/20, 357/23.13, 357/34, 357/35, 357/86, 357/88, 357/90, 257/355, 257/356, 257/362, 257/363
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A bipolar transistor and a bipolar diode are provided at an input pad on an integrated circuit, in order to shunt potential surges caused by electrostatic discharge (ESD). The approach makes use of a bipolar and a diode clamp with an optimized reverse biased breakdown from collector to base to shunt excess current away from sensitive regions with even current distribution for minimal damage. In order to improve the ESD immunity of the positive going ESD with respect to V_SS, the reverse bias breakdowns of the diode and of the transistor'"'"'s functioning as a collector/base diode are reduced. This circuit provides a simple low cost approach for improving ESD protection, in a process which fits into most standard Cmos process flows with few or no added process steps.

Claims

1. A semiconductor integrated circuit having internal circuitry, the integrated circuit further comprising:

a) a bond pad connected to said internal circuitry

b) a substrate of a first conductivity type;

c) a first region of a second conductivity type within said substrate connected to said bond pad and to said internal circuitry via a conductor, said first region being sufficiently doped to form an ohmic contact with the conductor;

d) a second region of the first conductivity type, of greater conductivity than said substrate, in a junction region of said substrate and said first region;

e) a third region of the first conductivity type, of greater conductivity than said substrate, within said substrate, coupled to a substrate potential source;

f) a fourth region of the second conductivity type within said substrate coupled to a reference potential node, wherein said first region forms a collector of a lateral bipolar transistor, a portion of said substrate between said first region and said fourth region forms a base of the transistor, said fourth region forms an emitter of the transistor, and said junction region is a collector/base junction of the lateral bipolar transistor; and

the substrate is connected to a node other than the reference potential node.

2. A semiconductor structure for electrostatic discharge protection of an integrated circuit, comprising:

a p-type substrate forming a base of a lateral NPN transistor;

a first N+region within said substrate forming a collector of the NPN transistor and an ohmic contact region;

a second N+region within said substrate forming an emitter of the NPN transistor;

a p-type region within said substrate at a collector base N+/p- junction of the NPN transistor; and

a second P+region withing said substrate, wherein said first N+region is coupled to an input of the integrated circuit, said second N+region is connected to a ground potential node, and said P+region is coupled to a reference potential node,

wherein the reference potential node supplies a potential which is less than ground potential.

3. An integrated circuit having internal circuitry, the integrated circuit further comprising:

a) an input node connected to the internal circuitry;

b) a substrate of a first conductivity type;

c) a first region of a second conductivity type within said substrate, said first region coupled to said input node and to the internal circuitry;

d) a second region of the first conductivity type, of greater conductivity than said substrate, said second region in a junction region of said substrate and said first region;

e) a third region of the first conductivity type, also of greater conductivity than said substrate, said third region within said substrate and coupled to a substrate potential source; and

f) a fourth region of the second conductivity type and within said substrate, said fourth region coupled to a reference potential node which provides a potential other than the substrate potential, wherein said first region forms a collector of a lateral bipolar transistor, a portion of said substrate between said first region and said fourth region forms a base of the transistor, said fourth region forms an emitter of the transistor, and said junction region is a collector/base junction of the lateral bipolar transistor.

4. A semiconductor integrated circuit having internal circuitry, the integrated circuit further comprising:

a) a bond pad connected to said internal circuitry

b) a substrate of a first conductivity type;

c) a first region of a second conductivity type within said substrate connected to said bond pad and to said internal circuitry via a conductor, said first region being sufficiently doped to form an ohmic contact with the conductor;

d) a second region of the first conductivity type, of greater conductivity than said substrate, in a junction region of said substrate and said first region;

e) a third region of the first conductivity type, of greater conductivity than said substrate, within said substrate, coupled to a substrate potential source; and

f) a fourth region of the second conductivity type within said substrate coupled to a reference potential node, wherein said first region forms a collector of a lateral bipolar transistor, a portion of said substrate between said first region and said fourth region forms a base of the transistor, said fourth region forms an emitter of the transistor, and said junction region is a collector/base junction of the lateral bipolar transistor;

said second region is at a lateral and at a vertical junction region of said substrate and said first region whereby a vertical bipolar diode and a lateral bipolar transistor each have a reverse bias breakdown voltage dependent upon said second region.

5. An electrostatic discharge protection structure for an integrated circuit, comprising:

a) a semiconductor substrate of a first conductivity type forming a base of a transistor and a first portion of a diode;

b) a first region of a second conductivity type within said substrate, forming a lateral junction and a vertical junction with said substrate, coupled to an input of the integrated circuit, said first region forming a collector of the transistor and a second portion of the diode;

c) a second region of the second conductivity type within said substrate coupled to a reference potential node, forming an emitter of the transistor;

d) a third region of the first conductivity type, of greater conductivity than said substrate, located at the lateral junction and at the vertical junction.

6. An integrated circuit having internal circuitry, the integrated circuit further comprising:

a) an input node connected to the internal circuitry;

b) a substrate of a first conductivity type;

c) a first region of a second conductivity type within said substrate, said first region connected to said input node and to the internal circuitry;

d) a second region of the first conductivity type, of greater conductivity than said substrate, at a lateral and at a vertical junction region of said substrate and said first region;

e) a third region of the first conductivity type, of greater conductivity than said substrate, within said substrate, said third region coupled to a substrate potential source; and

f) a fourth region of the second conductivity type within said substrate, said fourth region coupled to a reference potential node, wherein said first region forms a collector of a lateral bipolar transistor, a portion of said substrate between said first region and said fourth region forms a base of the transistor, said fourth region forms an emitter of the transistor, and said junction region is a collector/base junction of the lateral bipolar transistor.

7. A semiconductor integrated circuit having internal circuitry, the integrated circuit further comprising:

a) a bond pad connected to said internal circuitry

b) a substrate of a first conductivity type;

c) a first region of a second conductivity type within said substrate connected to said bond pad and to said internal circuitry via a conductor, said first region being sufficiently doped to form an ohmic contact with the conductor;

d) a second region of the first conductivity type, of greater conductivity than said substrate, in a junction region of said substrate and said first region; and

e) a third region of the first conductivity type, of greater conductivity than said substrate, within said substrate coupled to a substrate potential source; and

f) a series resistor interposed between the bond pad and the internal circuitry, the series resistor comprises;

a) a first resistor connected in series between said first region and the bond pad; and

b) a second resistor, having a resistance greater than said first resistor, connected in series between said first region and said internal circuitry.

8. A semiconductor integrated circuit having internal circuitry, the integrated circuit further comprising:

a) an input node connected to the internal circuitry;

b) a substrate region of a first conductivity type;

c) a first highly doped region of a second conductivity type adjacent said substrate region, coupled to said input node and to the internal circuitry;

d) a second region of the first conductivity type, of greater conductivity than said substrate, in a junction region of said substrate region and said first region; and

e) a third highly doped region of the first conductivity type, adjacent said substrate region, coupled to a substrate potential source, wherein a current flows between said input node and the substrate potential source through said second region when a voltage across the junction region exceeds a first potential, and the current ceases to flow when the voltage across the junction falls below the first potential.