Digital signal comparison circuit in a performance monitoring and test system

• US 5,581,228 A
• Filed: 05/26/1995
• Issued: 12/03/1996
• Est. Priority Date: 04/02/1992
• Status: Expired due to Term

• Current Assignee: Viavi Solutions, Inc. (Lumentum Holdings Inc.)
• Original Assignee: Applied Digital Access, Inc. (Lumentum Holdings Inc.)
• Inventors: Hartmann, Paul R., Cadieux, Kevin, Pope, Kevin
• Primary Examiner(s): Wamach, Margaret R.
• Application Number:
  US08/451,170
• Time in Patent Office: 557 Days
• Field of Search: 340/146.2, 377/39
• US Class Current: 340/146.2
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04J 3/0623 Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
• CPC Class Codes: H04J 3/14 Monitoring arrangements for SDH/SONET rings H04J3/085
• CPC Class Codes: H04M 3/22 Arrangements for supervision, monitoring or testing
• CPC Class Codes: H04M 3/244 for multiplex systems

Abstract

A DS3 level access, monitor and test system including a digital comparator for a telephone network. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

Claims

1. In a telephone network, a compare circuit for two digital signals, comprising:

a delay for one of the signals;

an m-bit shift register for receiving the signal from the delay;

an n-bit shift register for receiving the other signal; and

an m-bit comparator for simultaneously comparing each of the m-bits with one of the n bits,

wherein at least one of the signals is indicative of a signal in the telephone network.

2. The compare circuit defined in claim 1, wherein a comparison is made having up to the absolute value of m-n bits of latency between the two digital signals.

3. The compare circuit defined in claim 1, wherein the m-bit shift register is a seven bit shift register and the n-bit shift register is a four bit shift register.

4. The compare circuit defined in claim 1, wherein each digital signal comprises a DS3 signal.

5. The compare circuit defined in claim 1, additionally comprising a switch control circuit, receivably connected to the ouput of the m-bit comparator, to control which digital signal is processed by other circuits.

6. In a telephone network, a method for comparing two digital signals, comprising the steps of:

delaying one of the signals, received from the telephone network;

storing m bits of the delayed signal;

storing n bits of the other signal;

simultaneously comparing each of the m bits with one of the n bits; and

generating a compare signal based upon the comparison.

7. The method defined in claim 6, wherein the m-bit shift register is a seven bit shift register and the n-bit shift register is a four bit shift register.

8. The method defined in claim 6, wherein each digital signal comprises a DS3 signal.

9. The method defined in claim 6, wherein a hitless switch is made between the signals.