Digital signal comparison circuit in a performance monitoring and test system
First Claim
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1. In a telephone network, a compare circuit for two digital signals, comprising:
- a delay for one of the signals;
an m-bit shift register for receiving the signal from the delay;
an n-bit shift register for receiving the other signal; and
an m-bit comparator for simultaneously comparing each of the m-bits with one of the n bits,wherein at least one of the signals is indicative of a signal in the telephone network.
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Abstract
A DS3 level access, monitor and test system including a digital comparator for a telephone network. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.
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Citations
9 Claims
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1. In a telephone network, a compare circuit for two digital signals, comprising:
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a delay for one of the signals; an m-bit shift register for receiving the signal from the delay; an n-bit shift register for receiving the other signal; and an m-bit comparator for simultaneously comparing each of the m-bits with one of the n bits, wherein at least one of the signals is indicative of a signal in the telephone network. - View Dependent Claims (2, 3, 4, 5)
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6. In a telephone network, a method for comparing two digital signals, comprising the steps of:
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delaying one of the signals, received from the telephone network; storing m bits of the delayed signal; storing n bits of the other signal; simultaneously comparing each of the m bits with one of the n bits; and generating a compare signal based upon the comparison. - View Dependent Claims (7, 8, 9)
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Specification