Implementation and method for a digital sigma-delta modulator

• US 5,581,253 A
• Filed: 08/03/1995
• Issued: 12/03/1996
• Est. Priority Date: 08/03/1995
• Status: Expired due to Term

• Current Assignee: Microsemi Semiconductor (U.S.) Inc. (Microchip Technology Incorporated)
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Brown, Glen W.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US08/510,139
• Time in Patent Office: 488 Days
• Field of Search: 341/143, 341/141, 341/76, 341/77, 345/247
• US Class Current: 341/144
• CPC Class Codes: G06F 3/16 Sound input; Sound output speech processing G10L
• CPC Class Codes: G10H 1/0066 using a MIDI interface
• CPC Class Codes: G10H 1/125 using a digital filter
• CPC Class Codes: G10H 2230/035 Power management, i.e. specific power supply solutions for electrophonic musical instruments, e.g. auto power shut-off, energy saving designs, power conditioning, connector design, avoiding inconvenient wiring
• CPC Class Codes: G10H 2240/311 MIDI transmission G10H2240/056 takes precedence
• CPC Class Codes: G10H 2250/191 Chebyshev polynomials, e.g. to provide filter coefficients for sharp rolloff filters Chebyshev filters G10H2250/091; Chebyshev windows G10H2250/271
• CPC Class Codes: G10H 2250/545 Aliasing, i.e. preventing, eliminating or deliberately using aliasing noise, distortions or artifacts in sampled or synthesised waveforms, e.g. by band limiting, oversampling or undersampling, respectively
• CPC Class Codes: G10H 2250/571 Waveform compression, adapted for music synthesisers, sound banks or wavetables audio compression G10L19/00
• CPC Class Codes: G10H 2250/611 Waveform decimation, i.e. integer division of the sampling rate for reducing the number of samples in a discrete-time signal, e.g. by low-pass anti-alias filtering followed by the actual downsampling
• CPC Class Codes: G10H 7/002 using a common processing for different operations or calculations, and a set of microinstructions (programme) to control the sequence thereof
• CPC Class Codes: H03M 7/3028 the quantiser being a single bit one
• CPC Class Codes: H03M 7/3035 with provisions for rendering the modulator inherently stable, e.g. by restricting the swing within the loop, by removing part of the zeroes using local feedback loops, by positioning zeroes outside the unit circle causing the modulator to operate in a chaotic regime

Abstract

Described herein is a digital sigma-delta modulator and method for converting a multi-bit digital input signal to a 1-bit digital output signal. The digital sigma-delta modulator performs a noise shaping filter function for a digital-to-analog circuit. A series of cascaded integration stages are implemented with a plurality of multiplexed adders which perform the integration functions.

Claims

1. A sigma-delta modulator for a digital-to-analog converter (DAC) circuit, comprising:

(a) a multi-bit digital input signal;

(b) a first multiplexer, having a plurality of inputs and an output, wherein said digital input signal is connected to one of said inputs of said first multiplexer;

(c) first adder, having a plurality of inputs and an output, wherein said first multiplexer output is connected to one of said plurality of first adder inputs;

(d) a coefficient decode circuit having an input, and having an output connected to another input of said first adder;

(e) a shift register, having an input and an output, wherein said output of said first adder is connected to said shift register input;

(f) a second adder, having a plurality of inputs and an output, wherein said shift register output is connected to one of said plurality of second adder inputs; and

wherein said output of said second adder is provided to a quantizer for output as a 1-bit digital output signal.

2. A digital sigma-delta modulator for converting a multi-bit digital input signal to a 1-bit digital output signal, comprising:

(a) a first device for selecting between said digital input signal and a signal output from a first serial configuration of data registers, wherein said selected signal is provided to a first adder;

(b) a feedback signal and a selected coefficient value being provided to said first adder to be summed with said selected signal;

(c) an output of said first adder being scaled before being provided to a second adder; and

(d) a second selecting device which selects between one of two signals output from a second serial configuration of data registers, wherein said selected one of two signals is provided to said second adder to be summed with said scaled first adder output signal;

wherein a 1-bit digital output signal is output from said second adder.

3. The modulator of claim 2, wherein said second adder output is provided to a quantizer.

4. The modulator of claim 3, wherein said quantizer comprises a flip-flop.

5. An oversampling digital sigma-delta modulator for a digital-to-analog converter circuit, comprising:

(a) a multi-bit digital input signal;

(b) a first group of serially connected data registers;

(c) a second group of serially connected data registers;

(d) a first multiplexer which selects between said multi-bit digital input signal and an output signal from a last register in said first group of serially connected data registers, wherein said signal selected by said first multiplexer is provided to an input of a first adder; and

(e) a second multiplexer which selects between an output signal from a last register in said second group of serially connected data registers and an output signal from an intermediate register within said second group of serially connected data registers, wherein said signal selected by said second multiplexer is provided to an input of a second adder;

wherein an output of said first adder is scaled and then provided to another input of said second adder; and

wherein an output of said second adder is provided to a quantizer for output as a 1-bit digital output signal.

6. The sigma-delta modulator of claim 5, wherein said quantizer comprises a flip-flop.

7. The sigma-delta modulator of claim 5, further comprising a coefficient decode circuit, having an input selectively connected to a first or a second data register, and having an output connected to another input of said first adder.

8. The sigma-delta modulator of claim 5, wherein said output of said second adder is also provided to a first register in said second group of serially connected data registers.

9. The sigma-delta modulator of claim 5, wherein said 1-bit digital output signal is provided to a first multiplexer which multiplies said 1-bit signal by a first coefficient and then provides the product of said multiplication as an input to a third multiplexer.

10. The sigma-delta modulator of claim 9, wherein said output signal from said last register in said first group of serially connected data registers is provided also as another input to said third multiplexer.

11. The sigma-delta modulator of claim 10, wherein an output of said third multiplexer is provided as an input to a third adder.

12. The sigma-delta modulator of claim 5, wherein said first and said second group of serially connected data registers each includes at least three data registers.

13. A method of converting a multi-bit digital input signal to a 1-bit digital output signal, using a digital filter, comprising the steps of:

(a) providing a set of cascaded integration stages;

(b) providing said set of integration stages with a multi-bit digital input signal and a 1-bit digital output signal;

(c) quantizing said 1-bit digital output signal;

(d) multiplying said quantized 1-bit digital output signal by a plurality of filter coefficients selected by a coefficient decode circuit;

(e) providing said multiplied plurality of coefficients to nodes disposed between individual integration stages within said set of integration stages.

14. The method of claim 13, wherein said step of multiplying is accomplished by 1-bit multiplication.

15. A method of converting a multi-bit digital input signal to a 1-bit digital output signal, comprising the steps of:

(a) providing a sigma-delta modulator filter having a multi-bit digital input signal, a 1-bit digital output signal and a plurality of sets of adders, wherein each set of adders calculates a sum of two data terms;

(b) scaling said sum of two data terms calculated by each said set of adders, wherein said scaling is accomplished by one or more shift registers; and

(c) adding a third data term to said scaled sum of two data terms for each said set of adders.

16. The method of claim 15, wherein said step of scaling for at least one said set of adders is accomplished by shifting said sum of two data terms.

17. The method of claim 15, further comprising the steps of quantizing said 1-bit digital output signal.

18. The method of claim 17, further comprising the step of multiplying said quantized 1-bit digital output signal by at least one filter coefficient to generate at least one filter product.

19. The method of claim 18, wherein at least one of said data terms being summed in at least one of said sets of adders comprises at least one said filter product.

20. The method of claim 15, further comprising the steps of:

(d) providing at least one additional single adder; and

(e) calculating a filter product with said at least one additional single adder by multiplying a feedback filter coefficient by a data feedback term output from an integration stage included in said sigma-delta modulator filter.

21. A method of converting a multi-bit digital input signal to a 1-bit digital output signal, using a digital sigma-delta modulator, comprising the steps of:

(a) inputting said multi-bit digital input signal;

(b) selecting between said input signal and a signal output from a first group of serially connected data registers;

(c) summing said selected signal with a feedback signal;

(d) scaling said added signal;

(e) summing said scaled signal with a first selected signal output from a second group of serially connected data registers;

(f) outputting said sum of said scaled and first selected signals from said sigma-delta modulator as a 1-bit digital output signal.

22. The method of claim 21, further comprising the steps of selecting between a signal output from said second group of serially connected data registers and a signal output from an intermediate register in said second group of data registers, and providing said selected signal as said signal output from said second group of serially connected data registers to be summed with said scaled signal.

23. The method of claim 21, further comprising the step of summing a selected coefficient value with said selected signal and said feedback signal.

24. The method of claim 21, wherein said step of scaling is accomplished by shifting said sum of said selected signal and said feedback signal a minimum of two bit places.

25. A digital sigma-delta modulator filter, comprising:

(a) a plurality of integration stages, including a filter output;

(b) a multi-bit digital input signal input to a first integration stage in said plurality of integration stages;

wherein said filter output is input to a quantizer, said quantizer including an output;

wherein said quantizer output comprises a 1-bit digital output signal; and

wherein said 1-bit output signal is multiplied by a filter coefficient, said filter coefficient is selected by a coefficient decode circuit, and then fedback to each of said plurality of integration stages.