Video timing signal generation circuit

• US 5,581,303 A
• Filed: 01/18/1995
• Issued: 12/03/1996
• Est. Priority Date: 01/18/1995
• Status: Expired due to Fees

• Current Assignee: Autodesk, Inc.
• Original Assignee: Radius, Inc. (Washington) (DXC Technology Company)
• Inventors: Djabbari, Ali, Gilbert, Douglas J.
• Primary Examiner(s): Peng, John K.
• Assistant Examiner(s): GRANT, CHRISTOPHER C
• Application Number:
  US08/374,134
• Time in Patent Office: 685 Days
• Field of Search: 348/500, 348/521, 348/522, 348/523, 348/524, 348/540, 348/546, 348/547, 348/548
• US Class Current: 348/524
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

A programmable CPU running at a video display rate, or a sub-multiple thereof, is used to generate the timings by loading control registers on the fly. In a preferred embodiment, a very reduced instruction set is used to generate VSYNC, HSYNC, and CSYNC signals. The CPU executes instructions out of an Instruction SRAM. The CPU'"'"'s main goal is to load a pair of backing registers before a down counter reaches the value of zero.

Claims

1. A video timing signal generation circuit comprising:

a plurality of control registers; and

a programmable CPU running at a particular frequency and generating timings by loading the control registers on the fly, wherein the plurality of control registers includes a down counter register, a pixel counter backing register, an output signal register and an output signal backing register.

2. The video timing signal generation circuit according to claim 1, wherein the output signal register drives CSYNC, VSYNC and HSYNC signals.

3. The video timing signal generation circuit according to claim 1, wherein the CPU executes a very reduced instruction set and ensures that the pixel counter backing register and the output signal backing register are loaded before the down counter register reaches a value of zero.

4. The video timing signal generation circuit according to claim 2, wherein the CPU executes a very reduced instruction set and ensures that the pixel counter backing register and the output signal backing register are loaded before the down counter register reaches a value of zero.

5. The video timing signal generation circuit according to claim 4, wherein the frequency at which the CPU is running is equal to a submultiple of the video display rate.

6. A video timing signal generation circuit, comprising:

a plurality of control registers; and

a programmable CPU, said programmable CPU being programmed to generate timing signals in response to a very reduced set of instructions, and to load the control registers with said timing signals, wherein said very reduced set of instructions consists of four instructions.

7. The circuit of claim 6, wherein said four instructions are a LOAD instructions, a CALL instruction, a CRET instruction, and CJMP instruction.