Method for interactively tailoring topography of integrated circuit layout in accordance with electromigration model-based minimum width metal and contact/via rules
First Claim
1. A method of manufacturing an integrated circuit architecture comprising the steps of:
- (a) preparing a preliminary layout of a topography of circuit devices and associated interconnect through which said integrated circuit architecture is to be formed in semiconductor material;
(b) analyzing the operation of said integrated circuit to derive circuit parameters for a selected operational condition in respective branches of said integrated circuit and storing the derived circuit parameters for the respective branches of said integrated circuit;
(c) using circuit parameters derived in step (b), interactively analyzing each respective branch of the topography of said preliminary layout to identify where, within said each respective branch of said topography, a selected characteristic of said each respective branch of said topography fails to satisfy a prescribed operational standard of said integrated circuit and, as said each respective branch is analyzed, storing information representative of respective failures of said selected characteristic to satisfy said prescribed operational standard of said integrated circuit;
(d) interactively modifying, as necessary, said selected characteristic of one or more portions of only that branch or those branches of said topography where step (c) has identified said selected characteristic as failing to satisfy said prescribed operational standard of said integrated circuit, so as to obtain a modified layout of said topography of circuit devices and associated interconnect through which said integrated circuit architecture is to be formed in semiconductor material; and
(e) forming said integrated circuit architecture in semiconductor material in accordance with the modified layout of said topography of circuit devices and associated interconnect obtained in step (d), and whereinsaid circuit parameters derived in step (b) correspond to maximum currents through respective branches of said preliminary layout, and wherein step (c) comprises analyzing the topography of said preliminary layout to identify where, within a branch of said layout, a dimension of any of a metal line, via or contact of said branch fails to be as large as necessary to prevent electromigration in said branch for a current as large as the maximum current through said branch over a prescribed temperature range, and wherein step (c) further comprises analyzing the topography of said preliminary layout in accordance with sets electromigration rules respectively associated with respective ones of metal lines, vias and contacts of which said branches are comprised, and wherein step (c) additionally comprises demarcating a branch of said preliminary layout, and using the maximum branch current associated with the demarcated branch, said set of electromigration rules and the physical topography of the branch, to determine the path of current flow through the branch and electromigration-specific attribute, through which a determination is made as to whether a dimension of one or more portions of metal, bias or contacts within said demarcated branch must be increased, in order to satisfy said prescribed operational standard of said integrated circuit and wherein in step (c), demarcating a branch of said preliminary layout comprises selecting spaced apart end points of said branch, merging successively adjacent portions of interconnect into an effectively continuous layer of interconnect and defining respective cut regions at said spaced apart ends of said branch.
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Accused Products
Abstract
An interactive electromigration rule-based topography layout adjustment methodology is provided as an adjunct to a computer aided design tool, in particular a design rule check (DRC) mechanism, the engine for which is served by a design rule database for defining topography parameters that conform with a given semiconductor wafer fabrication process. Using a set of customized design rule statements, the DRC program is able to provide circuit designer with the ability to identify and interactively change, as necessary, dimensions of those portions of branches of interconnect (metal, contacts, vias) within the topography of an integrated circuit layout, the customized DRC statements being customized in accordance with circuit operation-derived worst case current conditions as applied to a prescribed set of electromigration-based minimum width rules for interconnect metal, contacts and vias.
131 Citations
25 Claims
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1. A method of manufacturing an integrated circuit architecture comprising the steps of:
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(a) preparing a preliminary layout of a topography of circuit devices and associated interconnect through which said integrated circuit architecture is to be formed in semiconductor material; (b) analyzing the operation of said integrated circuit to derive circuit parameters for a selected operational condition in respective branches of said integrated circuit and storing the derived circuit parameters for the respective branches of said integrated circuit; (c) using circuit parameters derived in step (b), interactively analyzing each respective branch of the topography of said preliminary layout to identify where, within said each respective branch of said topography, a selected characteristic of said each respective branch of said topography fails to satisfy a prescribed operational standard of said integrated circuit and, as said each respective branch is analyzed, storing information representative of respective failures of said selected characteristic to satisfy said prescribed operational standard of said integrated circuit; (d) interactively modifying, as necessary, said selected characteristic of one or more portions of only that branch or those branches of said topography where step (c) has identified said selected characteristic as failing to satisfy said prescribed operational standard of said integrated circuit, so as to obtain a modified layout of said topography of circuit devices and associated interconnect through which said integrated circuit architecture is to be formed in semiconductor material; and (e) forming said integrated circuit architecture in semiconductor material in accordance with the modified layout of said topography of circuit devices and associated interconnect obtained in step (d), and wherein said circuit parameters derived in step (b) correspond to maximum currents through respective branches of said preliminary layout, and wherein step (c) comprises analyzing the topography of said preliminary layout to identify where, within a branch of said layout, a dimension of any of a metal line, via or contact of said branch fails to be as large as necessary to prevent electromigration in said branch for a current as large as the maximum current through said branch over a prescribed temperature range, and wherein step (c) further comprises analyzing the topography of said preliminary layout in accordance with sets electromigration rules respectively associated with respective ones of metal lines, vias and contacts of which said branches are comprised, and wherein step (c) additionally comprises demarcating a branch of said preliminary layout, and using the maximum branch current associated with the demarcated branch, said set of electromigration rules and the physical topography of the branch, to determine the path of current flow through the branch and electromigration-specific attribute, through which a determination is made as to whether a dimension of one or more portions of metal, bias or contacts within said demarcated branch must be increased, in order to satisfy said prescribed operational standard of said integrated circuit and wherein in step (c), demarcating a branch of said preliminary layout comprises selecting spaced apart end points of said branch, merging successively adjacent portions of interconnect into an effectively continuous layer of interconnect and defining respective cut regions at said spaced apart ends of said branch. - View Dependent Claims (2)
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3. A method of manufacturing an integrated circuit architecture comprising the steps of:
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(a) preparing a preliminary layout of a topography of circuit devices and associated interconnect through which said integrated circuit architecture is to be formed in semiconductor material; (b) analyzing the operation of said integrated circuit to derive circuit parameters for a selected operational condition in respective branches of said integrated circuit and storing the derived circuit parameters for the respective branches of said integrated circuit; (c) using circuit parameters derived in step (b), interactively analyzing each respective branch of the topography of said preliminary layout to identify where, within said each respective branch of said topography, a selected characteristic of said each respective branch of said topography fails to satisfy a prescribed operational standard of said integrated circuit and, as said each respective branch is analyzed, storing information representative of respective failures of said selected characteristic to satisfy said prescribed operational standard of said integrated circuit; (d) interactively modifying, as necessary, said selected characteristic of one or more portions of only that branch or those branches of said topography where step (c) has identified said selected characteristic as failing to satisfy said prescribed operational standard of said integrated circuit, so as to obtain a modified layout of said topography of circuit devices and associated interconnect through which said integrated circuit architecture is to be formed in semiconductor material; and (e) forming said integrated circuit architecture in semiconductor material in accordance with the modified layout of said topography of circuit devices and associated interconnect obtained in step (d), and wherein said circuit parameters derived in step (b) correspond to maximum currents through respective branches of said preliminary layout, and wherein step (c) comprises analyzing the topography of said preliminary layout to identify where, within a branch of said layout, a dimension of any of a metal line, via or contact of said branch fails to be as large as necessary to prevent electromigration in said branch for a current as large as the maximum current through said branch over a prescribed temperature range, and wherein step (c) further comprises analyzing the topography of said preliminary layout in accordance with sets of electromigration rules respectively associated with respective ones of metal lines, vias and contacts of which said branches are comprises, and wherein step (c) additionally comprises demarcating a branch of said preliminary layout, and using the maximum branch current associated with the demarcated branch, said set of electromigration rules and the physical topography of the branch, to determine the path of current flow through the branch and electromigration-specific attributes, through which a determination is made as to whether a dimension of one or more portions of metal, bias or contacts within said demarcated branch must be increased, in order to satisfy said prescribed operational standard of said integrated circuit and wherein step (c) further comprises defining a set of cut regions at spaced apart end points of said branch, between which cut regions said branch is extracted from said topography, defining geometrical attributes of respective interconnect portions of which said extracted branch is comprised in accordance with electromigration rules respectively associated with materials of said respective interconnect portions, measuring attributes of contacts within said extracted branch, and determining the direction of current flow through said branch.
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4. A method of manufacturing an integrated circuit architecture comprising the steps of:
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(a) preparing a preliminary layout of a topography of circuit devices and associated interconnect material through which said integrated circuit architecture is formed in a semiconductor material; (b) analyzing the operation of said integrated circuit to derive circuit parameters for a selected operational condition in respective branches of said integrated circuit and storing the derived circuit parameters for the respective branches of said integrated circuit; (c) demarcating the topography of each branch of the circuit layout and, using circuit parameters derived in step (b), setting the maximum current through said each branch of the demarcated topography; (d) compiling and storing a set of customized Design Rule Check (DRC) statements that are customized in accordance with said demarcated topography of said each branch, the maximum current through said each branch, and electromigration rules for respective interconnect materials of which said each branch is comprised (e) executing a design rule check process using the customized DRC statements compiled and stored in step (d), in order to determine the width of interconnect material perpendicular to the direction of current flow, and generating an electromigration error region on a plot of said demarcated topography of said each branch, in response to interconnect material having a width less than the minimum width required by an electromigration rule set; (f) interactively modifying dimensions of said demarcated topography of only that branch or those branches for which said electromigration error region has been generated in step (e) so as to create a modified layout in which dimensions of associated interconnect, containing metal, contact and via regions, satisfy associated electromigration rule sets; and (g) forming said integrated circuit architecture in said semiconductor material in accordance with the interactively modified layout of said topography of circuit devices and associated interconnect created in step (f). - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of manufacturing an integrated circuit architecture comprising the steps of:
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(a) generating an integrated circuit architecture topography layout of circuit devices and associated interconnect material through which said circuit devices are to be interconnected to implement a circuit to be manufactured; (b) simulating the operation of said circuit in accordance with varying circuit operating conditions, so as to produce, for respective branches of said circuit, values of circuit parameters that result from said varying circuit operating conditions; (c) storing the values of circuit parameters produced in step (b); (d) comparing the values of circuit parameters stored in step (c) with design values of said circuit parameters; (e) specifying values of circuit parameters for each branch of said circuit based upon step (d); (f) for respective branches of said integrated circuit architecture topography layout, generating respective customized design rule check statements in accordance with; 1) physical attributes of said respective branches of said integrated circuit architecture topography layout, 2) values of circuit parameters for said respective branches of said integrated circuit architecture topography layout specified in step (e), and 3) electromigration rules for interconnect material in said respective branches of said integrated circuit architecture topography layout; (g) subjecting said integrated circuit architecture topography layout to a design rule check routine executed in accordance with the customized design rule check statements generated in step (f); (h) displaying said integrated circuit architecture topography layout; (i) demarcating regions of said integrated circuit architecture topography layout displayed in step (h) where execution of said design rule check routine in step (g) has determined that said integrated circuit architecture topography layout fails to comply with said electromigration rules; (j) interactively adjusting aspects of branches of said integrated circuit architecture topography layout containing regions demarcated in step (i), so as to produce a modified version of said integrated circuit architecture topography layout in which branches containing said regions demarcated in step (i) do not fail to comply with said electromigration rules; and (k) forming said modified version of said integrated circuit architecture topography layout derived in step (l) in semiconductor material. - View Dependent Claims (22, 23, 24, 25)
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Specification