Method for interactively tailoring topography of integrated circuit layout in accordance with electromigration model-based minimum width metal and contact/via rules

• US 5,581,475 A
• Filed: 08/13/1993
• Issued: 12/03/1996
• Est. Priority Date: 08/13/1993
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Majors, Steven S.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US08/106,251
• Time in Patent Office: 1,208 Days
• Field of Search: 364/488-491, 364/578, 371/22.1, 371/23, 371/29.1, 307/440, 307/465.1, 307/482.1
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

An interactive electromigration rule-based topography layout adjustment methodology is provided as an adjunct to a computer aided design tool, in particular a design rule check (DRC) mechanism, the engine for which is served by a design rule database for defining topography parameters that conform with a given semiconductor wafer fabrication process. Using a set of customized design rule statements, the DRC program is able to provide circuit designer with the ability to identify and interactively change, as necessary, dimensions of those portions of branches of interconnect (metal, contacts, vias) within the topography of an integrated circuit layout, the customized DRC statements being customized in accordance with circuit operation-derived worst case current conditions as applied to a prescribed set of electromigration-based minimum width rules for interconnect metal, contacts and vias.

Claims

1. A method of manufacturing an integrated circuit architecture comprising the steps of:

(a) preparing a preliminary layout of a topography of circuit devices and associated interconnect through which said integrated circuit architecture is to be formed in semiconductor material;

(b) analyzing the operation of said integrated circuit to derive circuit parameters for a selected operational condition in respective branches of said integrated circuit and storing the derived circuit parameters for the respective branches of said integrated circuit;

(c) using circuit parameters derived in step (b), interactively analyzing each respective branch of the topography of said preliminary layout to identify where, within said each respective branch of said topography, a selected characteristic of said each respective branch of said topography fails to satisfy a prescribed operational standard of said integrated circuit and, as said each respective branch is analyzed, storing information representative of respective failures of said selected characteristic to satisfy said prescribed operational standard of said integrated circuit;

(d) interactively modifying, as necessary, said selected characteristic of one or more portions of only that branch or those branches of said topography where step (c) has identified said selected characteristic as failing to satisfy said prescribed operational standard of said integrated circuit, so as to obtain a modified layout of said topography of circuit devices and associated interconnect through which said integrated circuit architecture is to be formed in semiconductor material; and

(e) forming said integrated circuit architecture in semiconductor material in accordance with the modified layout of said topography of circuit devices and associated interconnect obtained in step (d), and wherein

said circuit parameters derived in step (b) correspond to maximum currents through respective branches of said preliminary layout, and wherein step (c) comprises analyzing the topography of said preliminary layout to identify where, within a branch of said layout, a dimension of any of a metal line, via or contact of said branch fails to be as large as necessary to prevent electromigration in said branch for a current as large as the maximum current through said branch over a prescribed temperature range, and wherein step (c) further comprises analyzing the topography of said preliminary layout in accordance with sets electromigration rules respectively associated with respective ones of metal lines, vias and contacts of which said branches are comprised, and wherein step (c) additionally comprises demarcating a branch of said preliminary layout, and using the maximum branch current associated with the demarcated branch, said set of electromigration rules and the physical topography of the branch, to determine the path of current flow through the branch and electromigration-specific attribute, through which a determination is made as to whether a dimension of one or more portions of metal, bias or contacts within said demarcated branch must be increased, in order to satisfy said prescribed operational standard of said integrated circuit and wherein in step (c), demarcating a branch of said preliminary layout comprises selecting spaced apart end points of said branch, merging successively adjacent portions of interconnect into an effectively continuous layer of interconnect and defining respective cut regions at said spaced apart ends of said branch.

2. A method according to claim 1, wherein, in demarcating a branch of said preliminary layout respective cut region at said spaced apart ends of said branch are defined in accordance with the geometrical configuration of said branch adjacent to said end points.

3. A method of manufacturing an integrated circuit architecture comprising the steps of:

(a) preparing a preliminary layout of a topography of circuit devices and associated interconnect through which said integrated circuit architecture is to be formed in semiconductor material;

(b) analyzing the operation of said integrated circuit to derive circuit parameters for a selected operational condition in respective branches of said integrated circuit and storing the derived circuit parameters for the respective branches of said integrated circuit;

(c) using circuit parameters derived in step (b), interactively analyzing each respective branch of the topography of said preliminary layout to identify where, within said each respective branch of said topography, a selected characteristic of said each respective branch of said topography fails to satisfy a prescribed operational standard of said integrated circuit and, as said each respective branch is analyzed, storing information representative of respective failures of said selected characteristic to satisfy said prescribed operational standard of said integrated circuit;

(d) interactively modifying, as necessary, said selected characteristic of one or more portions of only that branch or those branches of said topography where step (c) has identified said selected characteristic as failing to satisfy said prescribed operational standard of said integrated circuit, so as to obtain a modified layout of said topography of circuit devices and associated interconnect through which said integrated circuit architecture is to be formed in semiconductor material; and

(e) forming said integrated circuit architecture in semiconductor material in accordance with the modified layout of said topography of circuit devices and associated interconnect obtained in step (d), and wherein

said circuit parameters derived in step (b) correspond to maximum currents through respective branches of said preliminary layout, and wherein step (c) comprises analyzing the topography of said preliminary layout to identify where, within a branch of said layout, a dimension of any of a metal line, via or contact of said branch fails to be as large as necessary to prevent electromigration in said branch for a current as large as the maximum current through said branch over a prescribed temperature range, and wherein step (c) further comprises analyzing the topography of said preliminary layout in accordance with sets of electromigration rules respectively associated with respective ones of metal lines, vias and contacts of which said branches are comprises, and wherein step (c) additionally comprises demarcating a branch of said preliminary layout, and using the maximum branch current associated with the demarcated branch, said set of electromigration rules and the physical topography of the branch, to determine the path of current flow through the branch and electromigration-specific attributes, through which a determination is made as to whether a dimension of one or more portions of metal, bias or contacts within said demarcated branch must be increased, in order to satisfy said prescribed operational standard of said integrated circuit and wherein step (c) further comprises defining a set of cut regions at spaced apart end points of said branch, between which cut regions said branch is extracted from said topography, defining geometrical attributes of respective interconnect portions of which said extracted branch is comprised in accordance with electromigration rules respectively associated with materials of said respective interconnect portions, measuring attributes of contacts within said extracted branch, and determining the direction of current flow through said branch.

4. A method of manufacturing an integrated circuit architecture comprising the steps of:

(a) preparing a preliminary layout of a topography of circuit devices and associated interconnect material through which said integrated circuit architecture is formed in a semiconductor material;

(b) analyzing the operation of said integrated circuit to derive circuit parameters for a selected operational condition in respective branches of said integrated circuit and storing the derived circuit parameters for the respective branches of said integrated circuit;

(c) demarcating the topography of each branch of the circuit layout and, using circuit parameters derived in step (b), setting the maximum current through said each branch of the demarcated topography;

(d) compiling and storing a set of customized Design Rule Check (DRC) statements that are customized in accordance with said demarcated topography of said each branch, the maximum current through said each branch, and electromigration rules for respective interconnect materials of which said each branch is comprised

(e) executing a design rule check process using the customized DRC statements compiled and stored in step (d), in order to determine the width of interconnect material perpendicular to the direction of current flow, and generating an electromigration error region on a plot of said demarcated topography of said each branch, in response to interconnect material having a width less than the minimum width required by an electromigration rule set;

(f) interactively modifying dimensions of said demarcated topography of only that branch or those branches for which said electromigration error region has been generated in step (e) so as to create a modified layout in which dimensions of associated interconnect, containing metal, contact and via regions, satisfy associated electromigration rule sets; and

(g) forming said integrated circuit architecture in said semiconductor material in accordance with the interactively modified layout of said topography of circuit devices and associated interconnect created in step (f).

5. A method according to claim 4, wherein demarcating the topography of a branch of the circuit layout in step (c) comprises designating respective locations at opposite ends of said branch, so as to place end boundaries of said branch and cut regions that enable said branch to be separated from the remainder of the interconnect material of the circuit topography.

6. A method according to claim 5, wherein step (c) comprises, for a selected end point, identifying interconnect material directly beneath coordinates of the end point to establish a `data` layer of the identified interconnect material, and merging multiple interconnect media that overlap or abut one another in the vicinity of the selected end point, so as to define a continuum of interconnect material, and generating an electromigration rule associated with the interconnect material that has been denoted as the data layer beneath the end point.

7. A method according to claim 6, wherein step (c) further comprises selecting an arbitrary point on said branch between end points of said branch, identifying the type of interconnect material directly beneath said arbitrary point, specifying the electromigration rule associated with the identified type of material and creating, from an associated material parameter list, a label to identify a composite set of materials of which said branch is formed.

8. A method according to claim 5, wherein step (d) comprises creating cut statements for metal and for identifying all contact material that resides within the branch of interest, through the execution of which cut statements the branch is severed from the remainder of the interconnect topography.

9. A method according to claim 8, wherein step (d) comprises generating cut statements for metal by logically combining all metals in electromigration parameter listings that correspond to the demarcated branch into a composite metal layer and excluding from the composite metal layer that portion of the interconnect metal corresponding to the cut regions.

10. A method according to claim 9, wherein step (d) further comprises creating cut statements for identifying all of the contact material that resides with said branch of interest by combining all of the contact material of a respective layer into composite contact material, and logically combining the composite contact material with contact material within said branch of interest.

11. A method according to claim 10, wherein step (d) further comprises generating connectivity extraction statements that serve to link each material of which the severed branch is comprised.

12. A method according to claim 11, wherein step (d) further comprises creating contact measurement statements by examining the differential spacing between the edges of contacts and overlapping metal, and the separation among adjacent contacts, in order to eliminate those edges of a contact or via that are effectively parallel to the direction of current flow and to employ only edges that are perpendicular to current flow.

13. A method according to claim 12, wherein step (d) comprises examining the degree of overlap of metal relative to contact material and comparing the degree of overlap with a prescribed value, as dictated by topography design rules to establish the principal direction of current flow relative to the edges of the contact.

14. A method according to claim 13, wherein step (d) comprises, in response to said degree of overlap being greater than a prescribed multiple of minimum overlap, establishing that the amount of metal alongside the contact is sufficient to cause most of the current flowing in the vicinity of the contact to be parallel to the major direction of current flow along the metal approaching the contact and, in response to the degree of overlap being less than or equal to said prescribed multiple of minimum overlap, establishing that sufficient current flows into the edge of the contact perpendicular to the major direction of current flow, so that the dimensions of the edge of the contact must be evaluated in accordance with an electromigration rule set.

15. A method according to claim 14, wherein step (d) comprises, in response to the degree of overlap being less than or equal to said prescribed multiple of minimum overlap, generating a region of the overlapping metal along the side edge of the contact as overlap metal, and excluding any contact edge contiguous with an overlapping region from electromigration rule analysis, while subjecting the dimension of the contact edge orthogonal to the excluded edge to a minimum dimension required by the associated electromigration rule.

16. A method according to claim 15, wherein step (d) further comprises growing edges of a respective contact by a prescribed minimum grid width to produce a set of boundary areas and, in response to overlap regions totally enclosing said grown boundary areas, excluding the corresponding edges of a respective contact from electromigration analysis, and excluding those portions of interconnect metal that are contiguous with edges of the contact, so as to leave a contact edge which is perpendicular to the direction of current flow.

17. A method according to claim 16, wherein step (d) further comprises growing each of a plurality of contacts that are spaced apart from one another by no more than a prescribed minimum overlap as specified in associated electromigration models, so that adjacent contacts that are within a minimum overlap separation from one another will effectively grow together and form a single enlarged contact.

18. A method according to claim 11, wherein step (d) further comprises creating metal verification statements based upon plotting edges of metal of the severed branch that are not coincident with previously cut metal layer edges and which have a width less than minimum metal width for said of the metal severed branch and generating an indication of the degree of error in width of said metal from minimum metal width.

19. A method according to claim 18, wherein step (e) comprises executing said design rule check process using the customized DRC statements compiled in step (d), and thereby determining the width of interconnect material perpendicular to the direction of current flow, and generating electromigration error regions on a plot of said demarcated branch, in response to interconnect material having a width less than the minimum width required by an associated electromigration model, and graphically highlighting error regions at those locations of the topography branch where electromigration failures will occur.

20. A method according to claim 19, wherein step (f) comprises modifying, as necessary, one or more portions of each branch of said topography where step (e) has highlighted locations of said each branch as failing to satisfy a prescribed operational standard of said integrated circuit, so as to obtain a modified layout of said topography of circuit devices and associated interconnect through which said integrated circuit architecture is formed in semiconductor material.

21. A method of manufacturing an integrated circuit architecture comprising the steps of:

(a) generating an integrated circuit architecture topography layout of circuit devices and associated interconnect material through which said circuit devices are to be interconnected to implement a circuit to be manufactured;

(b) simulating the operation of said circuit in accordance with varying circuit operating conditions, so as to produce, for respective branches of said circuit, values of circuit parameters that result from said varying circuit operating conditions;

(c) storing the values of circuit parameters produced in step (b);

(d) comparing the values of circuit parameters stored in step (c) with design values of said circuit parameters;

(e) specifying values of circuit parameters for each branch of said circuit based upon step (d);

(f) for respective branches of said integrated circuit architecture topography layout, generating respective customized design rule check statements in accordance with;

1) physical attributes of said respective branches of said integrated circuit architecture topography layout,

2) values of circuit parameters for said respective branches of said integrated circuit architecture topography layout specified in step (e), and

3) electromigration rules for interconnect material in said respective branches of said integrated circuit architecture topography layout;

(g) subjecting said integrated circuit architecture topography layout to a design rule check routine executed in accordance with the customized design rule check statements generated in step (f);

(h) displaying said integrated circuit architecture topography layout;

(i) demarcating regions of said integrated circuit architecture topography layout displayed in step (h) where execution of said design rule check routine in step (g) has determined that said integrated circuit architecture topography layout fails to comply with said electromigration rules;

(j) interactively adjusting aspects of branches of said integrated circuit architecture topography layout containing regions demarcated in step (i), so as to produce a modified version of said integrated circuit architecture topography layout in which branches containing said regions demarcated in step (i) do not fail to comply with said electromigration rules; and

(k) forming said modified version of said integrated circuit architecture topography layout derived in step (l) in semiconductor material.

22. A method according to claim 21, wherein step (k) comprises repeating steps (b)-(j), as necessary, to derive a finalized version of said integrated circuit architecture topography layout in which every branch thereof complies with said electromigration rules, and forming said finalized version of said integrated circuit architecture topography in semiconductor material.

23. A method according to claim 22, wherein step (b) comprises simulating the operation of said circuit in accordance with varying circuit operating conditions, so as to produce, for respective branches of said circuit, values of maximum current that result from said varying circuit operating conditions.

24. A method according to claim 23, wherein step (j) comprises interactively adjusting dimensions of one or more portions of branches of said integrated circuit architecture topography so as to produce a modified version of said integrated circuit architecture topography layout which does not fail to comply with said electromigration rules at said regions demarcated in step (i).

25. A method according to claim 24, wherein step (c) comprises storing the values of maximum currents produced in step (b), step (d) comprises comparing the values of maximum currents stored in step (c) with maximum design current values, and step (e) comprises specifying a value of maximum current for each branch of said circuit as the larger of maximum current stored in step (c) and the maximum design current value for said each branch.