Performance monitor for digital computer system

• US 5,581,482 A
• Filed: 04/26/1994
• Issued: 12/03/1996
• Est. Priority Date: 04/26/1994
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Wiedenman, Gregory B., DeGarmo, Randy L.
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): Assouad, Patrick J.
• Application Number:
  US08/233,138
• Time in Patent Office: 952 Days
• Field of Search: 364/550, 364/551.01, 395/575
• US Class Current: 702/186
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3495 for systems

Abstract

An apparatus for monitoring the performance of a computer system. A number of performance monitoring hardware elements may be placed throughout a computer system to simultaneously monitor the performance of a number of distinct components within the computer system. An advantage of the present invention over a software based approach is that the present invention allows any node within the computer system to be monitored. In addition, the present invention does not run on the systems CPU and therefore the performance monitoring function does not decrease system performance while operating. Finally, because the present invention does not run on the system'"'"'s CPU, the results of the performance monitoring function may be more accurate than a software base approach.

Claims

1. An apparatus for monitoring the performance of a computer system, the computer system having a maintenance controller and further having a plurality of preselected nodes wherein the computer system provides a number of signal values, sequenced in time, on a selected set of the plurality of preselected nodes, comprising:

a. a performance monitoring hardware element;

b. permanent interfacing means coupled to said performance monitoring hardware element for permanently interfacing said performance monitoring hardware element to the selected set of preselected modes within the computer system;

c. counting means coupled to said performance monitoring hardware element for determining an activity level by counting the number of times the computer system provides a predetermined sequence of signal values on the selected set of preselected nodes, over a predetermined period of time; and

d. providing means coupled to said counting means for providing the activity level to the maintenance controller.

2. An apparatus according to claim 1 wherein there is a plurality of performance monitoring hardware elements and a plurality of corresponding counting means within the computer system wherein each of the plurality of monitoring hardware elements and the plurality of corresponding counting means are coupled to a different selected set of the plurality of preselected nodes.

3. An apparatus according to claim 1 wherein the selected set of preselected nodes includes a program address bus of a microprocessor element in the computer system.

4. An apparatus for monitoring the performance of a computer system, the computer system having a maintenance controller and further having a microprocessor element, the microprocessor element having a program address bus wherein the microprocessor provides a number of address values, sequenced in time, on the program address bus, comprising:

a. a performance monitoring hardware element coupled to the program address hardware bus of the microprocessor element;

b. determining means coupled to said performance monitoring hardware element for determining when a predetermined set of the number of address values matches a predetermined sequence of address values;

c. counting means coupled to said determining means for determining an activity level by counting the number of times that said determining means determines a match over a predetermined period of time; and

d. providing means coupled to said counting means for providing the activity level to the maintenance controller.

20. An apparatus according to claim 4 wherein said predetermined address sequence is a predetermined address range.

5. An apparatus for monitoring the performance of a computer system, the computer system having a maintenance controller and further having a microprocessor element, the microprocessor element having a program address, comprising:

a. a performance monitoring hardware element coupled to the program address bus of the microprocessor element;

b. first determining means coupled to said performance monitoring hardware element for determining when the program address of the microprocessor element matches a predetermined starting address;

c. second determining means coupled to said performance monitoring hardware element for determining when the program address of the microprocessor element matches a predetermined ending address;

d. counting means coupled to said first determining means and said second determining means for determining an activity level by counting the number of times said first determining means determines a match and subsequently said second determining means determines a match, over a predetermined period of time; and

e. providing means coupled to said counting means for providing the activity level to the maintenance controller.

6. An apparatus for monitoring the performance of a computer system, the computer system having a maintenance controller and further having a microprocessor element wherein the microprocessor element has a preselected program address bus, comprising:

a. a performance monitoring hardware element coupled to the preselected program address bus of the microprocessor element;

b. a first comparator coupled to said performance monitoring hardware element for comparing the program address of the microprocessor element with a predetermined starting address;

c. a second comparator coupled to said performance monitoring hardware element for comparing the program address of the microprocessor element with a predetermined second address;

d. a counter coupled to said first comparator and further coupled to said second comparator for determining an activity level by counting the number of times said first comparator determines a match between the program address and the predetermined first address and subsequently said second comparator determines a match between the program address and the predetermined second address, in a predetermined period of time; and

e. providing means coupled to said counter for providing the activity level to the maintenance controller.

7. An apparatus according to claim 6 further comprising:

e. a first masking circuit coupled to said first comparator for masking out a predetermined portion of the first comparator thus indicating a match for the predetermined portion of the first comparator; and

f. a second masking circuit coupled to said second comparator for masking out a predetermined portion of the second comparator thus indicating a match for the predetermined portion of the second comparator.

8. An apparatus for monitoring the performance of a computer system, the computer system having a microprocessor element and the microprocessor element having a program address, comprising:

a. a start address pointer register;

b. a start address mask register;

c. an end address pointer register;

d. an end address mask register;

e. a first dynamic write port hardware bus coupled to said start address pointer register for loading said start address pointer register with a first initial value;

f. a second dynamic write port hardware bus coupled to said start address mask register for loading said start address mask register with a second initial value;

g. a third dynamic write port hardware but coupled to said end address pointer register for loading said end address pointer register with a third initial value;

h. a fourth dynamic write port hardware bus coupled to said end address mask register for loading said end address mask register with a fourth initial value;

i. a first bit comparator coupled to said start address pointer register and further coupled to the program address for performing a bit-by-bit comparison of the first initial value and the program address and for providing a first result;

j. a second bit comparator coupled to said first bit comparator and further coupled to said start address mask register for performing a bit-by-bit comparison of the second initial value and the result of the first bit comparator thereby masking out predetermined bits from the comparison and for providing a second result;

k. a third bit comparator coupled to said end address pointer register and further coupled to the program address for performing a bit-by-bit comparison of the third initial value and the program address and for providing a third result;

l. a fourth bit comparator coupled to said first bit comparator and further coupled to said end address mask register for performing a bit-by-bit comparison of the fourth initial value and the result of the third bit comparator thereby masking out predetermined bits from the comparison and for providing a fourth result;

m. a program match register coupled to said second bit comparator and said fourth bit comparator wherein said program match register is set by the result of said second bit comparator and is cleared by the result of said fourth bit comparator;

n. an event counter coupled to said program match register for counting the number of times said program match register is set;

o. an event holding register couple to said event counter for periodically storing the value contained in the event counter;

p. a mode port, the mode port being asserted into a first state when in a single sample mode and the mode port being asserted into a second state when in a continuous sample mode; and

q. a interval counter coupled to said event counter and further coupled to said event holding register, the interval counter counting for a predetermined time period before enabling the event holding register to capture the value contained in the event counter, the interval counter also disabling the event counter and the interval counter when the mode port is asserted in said first state.

9. An apparatus for monitoring the performance of a computer system wherein the computer system has a maintenance controller and further has a plurality of preselected nodes wherein the operation of the computer system causes events to occur on said preselected nodes, comprising:

a. a plurality of test condition input ports, at least one of said plurality of test condition input ports being coupled to one of said plurality of preselected nodes in the computer system;

b. a condition selector multiplexer for selecting one of said plurality of test condition input ports;

c. an event counter coupled to said condition selector multiplexer for determining an activity level by counting the number of events that occur on said selected test condition input port;

d. an event holding register coupled to said event counter for periodically storing the activity level contained in the event counter;

e. a mode port, the mode port being asserted into a first state when in a single sample mode and the mode port being asserted into a second state when in a continuous sample mode;

f. an interval counter coupled to said event counter and further coupled to said event holding register, the interval counter counting for a predetermined time period before enabling the event holding register to capture the activity level contained in the event counter, the interval counter also disabling the event counter and the interval counter when the mode port is asserted in said first state; and

e. transferring means coupled to the event holding register for transferring the activity level from the event holding register to the maintenance controller.

10. A method for monitoring the performance of a computer system with a performance monitoring hardware element having a test condition input port which is coupled to a preselected node within the computer system, the computer system having a program address, comprising:

a. initializing the performance monitoring hardware element with initial values;

b. starting an interval timer;

c. comparing the program address to a start address pointer;

d. masking out a predetermined portion of the program address from the comparison in step (c) thereby effectively providing a match between the predetermined portion of the program address and the start address pointer;

e. incrementing an event counter if steps (c)-(d) indicate a match;

f. comparing the program address to an end address pointer;

g. masking out a predetermined portion of the program address from the comparison in step (f) thereby effectively providing a match between the predetermined portion of the program address and the end address pointer;

h. determining if the interval timer has expired and if the interval timer has not expired, returning to step (c);

i. interrupting steps (c)-(h) if the interval timer expires and then proceeding with step (j); and

j. processing the total number of events counted in step (e).

11. An apparatus for monitoring the performance of a computer system, the computer system having a maintenance controller and further having a plurality of preselected nodes wherein the computer system provides a number of signal values, sequenced in time, on a selected set of the plurality of preselected nodes, and wherein the computer system providing a sample period by asserting a sample period signal, comprising:

a. a performance monitoring hardware element;

b. permanent interfacing means coupled to said performance monitoring hardware element for permanently interfacing said performance monitoring hardware element to a selected one of the plurality of preselected nodes within the computer system;

c. counting means coupled to said performance monitoring hardware element for determining an activity level by counting the number of times the computer system provides a predetermined sequence of signal values on the selected set of preselected nodes during the sample period; and

d. providing means coupled to said counting means for providing the activity level to the maintenance controller.

12. An apparatus for monitoring the performance of a computer system, the computer system having a program address, comprising:

a. a performance monitoring means coupled to the computer system, said performance monitoring means having a test condition input port which is coupled to a preselected node within the computer system;

b. initializing means for initializing said performance monitoring means with initial values;

c. providing means coupled to said performance monitoring means for providing a predetermined sample period via a sample pulse;

d. first comparing means coupled to said performance monitoring means for comparing the program address to a start address pointer;

e. first masking means for masking out a predetermined portion of the program address from the first comparing means thereby effectively providing a match between the predetermined portion of the program address and the start address pointer;

f. incrementing means for incrementing an event counter if the first comparing means indicates a match;

g. second comparing means for comparing the program address to an end address pointer;

h. second masking means for masking out a predetermined portion of the program address from the comparing means thereby effectively providing a match between the predetermined portion of the program address and the end address pointer;

i. determining means for determining if the sample period has expired; and

j. processing means for processing the total number of events counted after the predetermined sample period expires.

13. An apparatus for monitoring the performance of a computer system, the computer system having a maintenance controller and further having a plurality of preselected nodes wherein the computer system provides a number of signal values, sequenced in time, on a selected set of the plurality of preselected nodes, and wherein the computer system providing a sample period by asserting a sample period signal, comprising:

a. a performance monitoring hardware element;

b. permanent interfacing means coupled to said performance monitoring hardware element for permanently interfacing said performance monitoring hardware element to the selected set of preselected nodes within the computer system;

c. counting means coupled to said performance monitoring hardware element for determining an activity level by counting the number of times the computer system provides a predetermined sequence of signal values on the selected set of preselected nodes, during the sample period; and

d. providing means coupled to said counting means for providing the activity level to the maintenance controller.

14. An apparatus according to claim 13 wherein the performance monitoring hardware element is coupled to a plurality of preselected nodes within the computer system.

15. An apparatus according to claim 14 wherein the performance monitoring hardware element is coupled to a program address bus of a microprocessor element in the computer system.

16. An apparatus for monitoring the performance of a computer system, the computer system having a maintenance controller and further having a microprocessor element wherein the microprocessor element has a program address bus, the microprocessor providing a number of address values sequenced in time, on the program address bus, and the microprocessor providing a sample period by asserting a sample period signal, comprising:

a. a performance monitoring hardware element coupled to the program address hardware bus of the microprocessor element;

b. first determining means coupled to said performance monitoring hardware element for determining when a first predetermined set of the number of address values matches a first predetermined sequence of address values;

c. first counting means coupled to said first determining means for determining a first activity level by counting the number of times that said first determining means determines a match during the sample period;

d. second determining means coupled to said performance monitoring hardware element for determining when a second predetermined set of the number of address values matches a second predetermined sequence of address values;

e. second counting means coupled to said second determining means for determining a second activity level by counting the number of times that said second determining means determines a match during the sample period;

f. first providing means coupled to said first counting means for providing the first activity level to the maintenance controller; and

g. second providing means coupled to said second counting means for providing the second activity level to the maintenance controller.

17. An apparatus for monitoring the performance of a computer system, the computer system having a maintenance controller and further having a microprocessor element wherein the microprocessor element has a preselected program address bus, comprising:

a. a performance monitoring hardware element coupled to the preselected program address bus of the microprocessor element;

b. first determining means coupled to said performance monitoring hardware element for determining when the program address of the microprocessor element matches a predetermined starting address;

c. second determining means coupled to said performance monitoring hardware element for determining when the program address of the microprocessor element matches a predetermined ending address;

d. counting means coupled to said first determining and further to said second determining means for determining an activity level by counting the number of times said first determining means determines a match and subsequently said second determining means determines a match, during the sample period; and

e. providing means coupled to said counting means for providing the activity level to the maintenance controller.

18. An apparatus for monitoring the performance of a computer system, the computer system having a maintenance controller and further having a microprocessor element wherein the microprocessor element has a preselected program address bus, comprising:

a. a performance monitoring hardware element coupled to the preselected program address hardware bus of the microprocessor element;

b. a comparator coupled to said performance monitoring hardware element for comparing the program address of the microprocessor element with a predetermined address;

c. a counter coupled to said comparator for determining an activity level by counting the number of times that said comparator determines a match between the program address and the predetermined address when an event is present during a sample pulse period;

d. a masking circuit coupled to said comparator for masking out a predetermined portion of the comparator thus indicating a match for the predetermined portion; and

e. providing means coupled to said counter for providing the activity level to the maintenance controller.

19. An apparatus for monitoring the performance of a computer system, the computer system having a maintenance controller and further having a microprocessor element wherein the microprocessor element has a preselected program address bus, the microprocessor providing a sample period by asserting a sample period signal, comprising:

a. a performance monitoring hardware element coupled to the preselected program address bus of the microprocessor element;

b. a first comparator coupled to said performance monitoring hardware element for comparing the program address of the microprocessor element with a predetermined starting address;

c. a second comparator coupled to said performance monitoring hardware element for comparing the program address of the microprocessor element with a predetermined second address;

d. a counter coupled to said first comparator and further coupled to said second comparator for determining an activity level by counting the number of times said first comparator determines a match between the program address and the predetermined first address and subsequently said second comparator determines a match between the program address and the predetermined second address, during the sample period; and

e. providing means coupled to said counter for providing the activity level to the maintenance controller.

21. A method for monitoring the performance of a computer system with a performance monitoring hardware element having a test condition input port which is coupled to a preselected node within the computer system, the computer system having a program address, comprising:

a. initializing the performance monitoring hardware element with initial values;

b. starting an interval timer;

c. comparing the program address to a start address pointer;

d. incrementing an event counter if steps (c) indicate a match;

e. returning to step (c) if step (c) does not indicate a match;

f. comparing the program address to an end address pointer;

g. returning to step (f) if step (f) does not indicate a match;

h. returning to step (c) of step (f) does indicate a match;

i. interrupting steps (c)-(h) if the interval timer expires and then proceeding with step (j); and

j. processing the total number of events counted in step (d).

22. An apparatus for monitoring the performance of a computer system, the computer system providing a number of time sequenced program addresses, comprising:

a. a performance monitoring means coupled to the computer system, said performance monitoring means having a test condition input port which is coupled to a preselected node within the computer system;

b. initializing means for initializing said performance monitoring means with initial values;

c. providing means coupled to said performance monitoring means for providing a predetermined sample period via a sample pulse;

d. first comparing means coupled to said performance monitoring means for comparing the number of time sequenced program addresses to a start address pointer;

e. incrementing means for incrementing an event counter if the first comparing means indicates a match between one of said time sequenced program addresses and said start address pointer, said incrementing means becoming disabled after incrementing the event counter;

f. second comparing means for comparing the number of time sequenced program addresses to an end address pointer, said second comparing means enabling said incrementing means if said second comparing means determines that one of the number of time sequenced program addresses matches said end address pointer;

g. determining means for determining if the sample period has expired; and

h. processing means for processing the total number of events counted during the predetermined sample period.