Memory cell with power supply induced reversed-bias pass transistors for reducing off-leakage current

• US 5,581,500 A
• Filed: 07/05/1995
• Issued: 12/03/1996
• Est. Priority Date: 12/16/1994
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: D'Souza, Godrey P.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US08/498,192
• Time in Patent Office: 517 Days
• Field of Search: 365/154, 365/184, 365/148, 365/189.01, 365/227, 365/228
• US Class Current: 365/156
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/418 Address circuits

Abstract

A memory cell is disclosed. The memory cell operating within a power supply range that induces the pass transistor(s) of the memory cell to be reversed biased when the memory cell is not being accessed. The memory cell includes a storage element capable of storing either a first data value or a second data value, a pass transistor, coupled to the storage element, and a power supply generator is coupled to the storage element. The power supply generator is configured to generate supply level voltages for the storage element so as to induce the pass transistor into a substantially reverse-biased state when the storage element is not being accessed, regardless of whether the storage element is storing the first data value or a second data value.

Claims

1. A memory cell, comprising:

a storage element capable of storing either a first data value or a second data value;

a pass transistor, coupled to the storage element; and

a power supply generator, coupled to the storage element, the power supply generator configured to provide a first power supply and a second power supply to the storage element when the storage element is being read, and the first power supply and a third power supply to the storage element so as to induce the pass transistor into a substantially reverse-biased state when the storage element is not being read, regardless of whether the storage element is storing the first data value or the second data value.

2. The memory cell of claim 1, wherein the storage element is a DRAM.

3. The memory cell of claim 2, wherein the first power supply is VDD and the third power supply is (VSS+Δ

).

4. The memory cell of claim 1, further comprising a word line driver circuit configured to drive a word line coupled to the pass transistor, the word line driver circuit configured to the drive the word line to a voltage potential of approximately VSS so that the pass transistor is maintained in a substantially reversed biased state when the storage element is not being accessed.

5. The memory cell of claim 4, wherein the word line driver is further configured to drive the word line coupled to the pass transistor to a voltage potential of approximately VDD to turn the the pass transistor on so that that the storage element can be accessed.

6. The memory cell of claim 1, wherein the second power supply is VSS.

7. The memory cell of claim 1, wherein the power supply generator comprises a circuit that is capable of providing the supply voltage of either VSS or (VSS+Δ

) depending on the state of the memory cell.

8. The memory cell of claim 1, wherein the storage element is an SRAM.

9. The memory cell of claim 1, wherein the power supply generator is configured to generate the first power supply and the third power supply when the storage element is not being accessed.

10. The memory cell of claim 1, wherein the power supply generator is configured to generate the first power supply and the third power supply when the storage element is being written.

11. The memory cell of claim 1, wherein the third supply voltage is between the first supply voltage and the second supply voltage.

12. The memory cell of claim 1, further comprising a plurality of the memory cells arranged in an array on a semiconductor chip.

13. The memory cell of claim 12, wherein the semiconductor chip is contained in a computer.

15. The process of claim 13, wherein the provided storage element is a DRAM.

16. The process of claim 13, wherein the provided storage element is an SRAM.

21. The memory cell of claim 7, wherein the circuit comprises:

a logic circuit coupled to receive a word line signal and an enable signal, and configured to generate the third power supply when the enable signal and the word line signal are logically true.

14. A method of providing a memory cell capable of operating in either a standby state or an access state, the method comprising:

providing a storage element capable of storing either a first data value or a second data value;

providing a pass transistor, coupled to the storage element; and

providing a power supply generator, coupled to the storage element, the power supply generator configured to provide a first power supply and a second power supply to the storage element when the storage element is being accessed, and the first power supply and a third power supply to the storage element so as to induce the pass transistor into a substantially reverse-biased state when the storage element is not being read, regardless of whether the storage element is storing the first data value or the second data value.

17. The process of claim 14, wherein the power supply generator is configured to generate the first power supply and the second power supply when the memory cell is being read and the first power supply and the third power supply when the memory cell is not being accessed or is being written.

18. A method of operating a memory cell capable of operating in either a standby state or an access state, the method comprising:

storing either a first data value or a second data value in a storage element having a pass transistor;

generating a first supply voltage and a second supply voltage for the storage element when the storage element is being read; and

generating the first supply voltage and a third supply voltage for the storage element which induces the pass transistor into a substantially reverse-biased state when the storage element is not being read, regardless of whether the storage element is storing the first data value or a second data value.

19. The process of claim 18, wherein the provided storage element is a DRAM.

20. The process of claim 18, wherein the provided storage element is an SRAM.