Non-volatile electrically erasable memory with PMOS transistor NAND gate structure
First Claim
1. A PMOS NAND memory string formed in an N-well, said string comprising:
- a P-channel string select transistor having a drain coupled to a bit line and having a source and a gate;
a P-channel ground select transistor having a source, a drain, and a gate; and
a plurality of series connected P-channel floating gate memory cells each having a source, a drain, and a control gate and being connected between said drain of said ground select transistor and said source of said string select transistor.
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Accused Products
Abstract
A NAND Flash EEPROM string is formed in a common N-well and includes a plurality of P-channel MOS stacked-gate storage transistors and P-channel MOS string and ground select transistors. In the preferred embodiment, each P-channel storage transistor is programmed via hot electron injection from the depletion region proximate its P drain/N-well junction and erased via electron tunneling from its floating gate to its P-type channel as well as to its P source and P drain regions without requiring high programming and erasing voltages, respectively. Further, high P/N junction biases are not required during programming or erasing operations. This allows the dimensions of the present embodiments to be reduced to a size smaller than that of comparable conventional N-channel NAND Flash EEPROM strings.
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Citations
15 Claims
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1. A PMOS NAND memory string formed in an N-well, said string comprising:
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a P-channel string select transistor having a drain coupled to a bit line and having a source and a gate; a P-channel ground select transistor having a source, a drain, and a gate; and a plurality of series connected P-channel floating gate memory cells each having a source, a drain, and a control gate and being connected between said drain of said ground select transistor and said source of said string select transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification