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Non-volatile electrically erasable memory with PMOS transistor NAND gate structure

  • US 5,581,504 A
  • Filed: 11/14/1995
  • Issued: 12/03/1996
  • Est. Priority Date: 11/14/1995
  • Status: Expired due to Term
First Claim
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1. A PMOS NAND memory string formed in an N-well, said string comprising:

  • a P-channel string select transistor having a drain coupled to a bit line and having a source and a gate;

    a P-channel ground select transistor having a source, a drain, and a gate; and

    a plurality of series connected P-channel floating gate memory cells each having a source, a drain, and a control gate and being connected between said drain of said ground select transistor and said source of said string select transistor.

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