Ram/ROM hybrid memory architecture
First Claim
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1. A memory cell, comprising:
- (a) a latch having a first node and a second node;
(b) a first pass transistor and a second pass transistor, said first pass transistor and said second pass transistor controlled by a first control line, said first pass transistor and said second pass transistor operable to electrically couple said first node and said second node of said latch to a respective bit line pair;
(c) at least one shorting element, with a first shorting element electrically coupled to said first node of said latch to pull said first node toward a constant potential; and
(d) said at least one shorting element including a fuse and a switching transistor, said switching transistor connected in series with said fuse.
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Abstract
An integrated circuit memory which includes at least some RAM/ROM hybrid columns. The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.
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Citations
7 Claims
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1. A memory cell, comprising:
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(a) a latch having a first node and a second node; (b) a first pass transistor and a second pass transistor, said first pass transistor and said second pass transistor controlled by a first control line, said first pass transistor and said second pass transistor operable to electrically couple said first node and said second node of said latch to a respective bit line pair; (c) at least one shorting element, with a first shorting element electrically coupled to said first node of said latch to pull said first node toward a constant potential; and (d) said at least one shorting element including a fuse and a switching transistor, said switching transistor connected in series with said fuse. - View Dependent Claims (2, 3, 4)
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5. A memory cell, comprising:
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(a) a latch having a first node and a second node; (b) a first pass transistor and a second pass transistor, said first pass transistor and said second pass transistor controlled by a first control line, said first pass transistor and said second pass transistor operable to electrically couple said first node and said second node of said latch to a respective bit line pair; (c) a plurality of nonvolatile shorting elements, with a first shorting element electrically coupled to said first node of said latch to pull said first node toward a constant potential, and a second shorting element electrically coupled to said second node of said latch to pull said second node toward a constant potential; (e) each of said plurality of nonvolatile shorting elements including a fuse; and (f) a switching transistor connected in series with said fuse; (g) wherein each of said switching transistors are commonly controlled by a second control line. - View Dependent Claims (6, 7)
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Specification