Method and apparatus to adaptively control the frequency of reception in a digital wireless communication system

• US 5,581,579 A
• Filed: 09/01/1995
• Issued: 12/03/1996
• Est. Priority Date: 08/17/1993
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: TCSI Corp. (Rocket Software Incorporated)
• Inventors: Subramanian, Ravi, Suzuki, Kenkichi, Lin, Nan-Sheng
• Primary Examiner(s): Tse, Young T.
• Application Number:
  US08/523,032
• Time in Patent Office: 459 Days
• Field of Search: 375/281, 375/283, 375/324-326, 375/330-331, 375/340, 375/343-345, 375/348, 329/304, 455/192.1, 455/192.2
• US Class Current: 375/331
• CPC Class Codes: H04L 27/152 using controlled oscillators, e.g. PLL arrangements
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

In a digital wireless communication system operating between a first unit and a second unit, the first unit transmits a digitally encoded RF signal at a first frequency in a plurality of a non-contiguous time slots to the second unit. The second unit receives the digitally encoded RF signals. The received RF digitally encoded signal is converted to an intermediate frequency (IF). An A to D converter samples the received IF digitally encoded signals and generates a plurality of discrete binary symbols during one of the plurality of non-contiguous time slots. A phase error signal is generated for each one of the plurality of discrete binary symbols. A frequency error signal is generated for the subsequent symbol in accordance with Δf(n+1)=Δf(n)+g₁ (⊖(n)-⊖(n)). The conversion of the RF signal to intermediate frequency is controlled in response to the frequency error signal. The control is adjusted after the one time slot but prior to the commencement of a subsequent one of the plurality of non-contiguous time slots.

Claims

1. An apparatus for receiving a digitally encoded signal transmitted wirelessly in a plurality of non-contiguous time slots by a first unit, said apparatus comprising:

antenna means for receiving said digitally encoded signal;

converting means, coupled to said antenna means, for converting the received digitally encoded signal, to a lower frequency;

sampling means for receiving the converted received digitally encoded signal at said lower frequency and for generating a plurality of discrete binary symbols during one of said plurality of non-contiguous time slots;

determining means for receiving each one of said plurality of discrete binary symbols (n) and for determining a phase error signal thereof and for generating a frequency error signal for the discrete binary symbol (n+1), subsequent to said one discrete binary symbol (n), in accordance with

space="preserve" listing-type="equation">Δ

f(n+1)=Δ

f(n)+g.sub.1 (⊖

(n)-⊖

(n))

where g₁ is a constant, (⊖

(n)-⊖

(n)) is said phase error signal for the nth symbol, Δ

f(n) is the frequency error signal for the nth symbol, and Δ

f(n+1) is the frequency error signal for the n+1 symbol; and

means for controlling said converting means in response to said frequency error signal after said one of said plurality of non-contiguous time slots but prior to the commencement of a non-contiguous time slot, subsequent thereto.

2. The apparatus of claim 1 wherein said digitally encoded signal in each of said non-contiguous time slots comprises synchronization signal followed by data signal.

3. The apparatus of claim 2 wherein said g₁ =2^-11 during a sync acquisition mode, and g₁ =2^-13 during a steady state mode.

4. The apparatus of claim 1 further comprising digital to analog converting means for receiving said frequency error signal and for converting it into an analog signal, supplied to said controlling means.

5. The apparatus of claim 1 wherein said determining means comprises:

first means for processing said plurality of discrete binary symbols;

second means for processing said plurality of discrete binary symbols by equalization; and

means for activating either said first or said second processing means.

6. The apparatus of claim 5 wherein said first processing means comprises:

fine pass filter means for receiving said plurality of discrete binary symbols and for filtering each symbol; and

differential detector means for receiving each filtered symbol and for generating an output symbol.

7. The apparatus of claim 6 wherein said second processing means comprises:

equalizer means for correcting interference between each of said plurality of discrete binary symbols, and for generating an output symbol one at a time.

8. The apparatus of claim 7 wherein said determining means further comprises:

phase slicer means for receiving said output symbol (n) and for generating a first phase signal ⊖

(n);

arc tangent means for receiving said output symbol (n) and for generating a second phase signal ⊖

(n); and

means for receiving the first phase signal ⊖

(n) and the second phase signal ⊖

(n) and for generating the phase error signal.

9. A method of operating a first unit for adjusting the carrier frequency received by said first unit in a wireless digital communication system operating between said first unit and a second unit wherein said second unit transmits a digitally encoded signal in a plurality of non-contiguous time slots to said first unit, said method comprising:

receiving said digitally encoded signal by said first unit;

converting the received digitally encoded signal to a lower frequency;

sampling said lower frequency received digitally encoded signal, during one of said plurality of non-contiguous time slots, to produce a plurality of discrete binary symbols;

storing said plurality of discrete binary symbols;

determining a phase error signal associated with one symbol (n) from said plurality of discrete binary symbols;

generating a frequency error signal for the symbol (n+1), subsequent to said one symbol (n), in accordance with

space="preserve" listing-type="equation">Δ

f(n+1)=Δ

f(n)+g.sub.1 (⊖

(n)-⊖

(n))

where g₁ is a constant, (⊖

(n)-⊖

(n)) is said phase error signal for the nth symbol, Δ

f(n) is the frequency error signal for the nth symbol, and Δ

f(n+1) is the frequency error signal for the n+1 symbol; and

adjusting said lower frequency in response to said frequency error signal after said one of said plurality of non-contiguous time slots but prior to a non-contiguous time slot subsequent thereto.

10. The method of claim 9 wherein said digitally encoded signal in each of said non-contiguous time slots comprises synchronization signal followed by data signal.

11. The method of claim 10 wherein said g₁ =2^-11 during a sync acquisition mode, and g₁ =2^-13 during a steady state mode.

12. The method of claim 9 further comprising:

converting the frequency error signal into an analog frequency error signal; and

adjusting said lower frequency in response to said analog frequency error signal.

13. The method of claim 9 wherein the determining step comprises:

processing said plurality of discrete binary symbols in accordance with either of the following processes;

I. receiving a symbol (n) and filtering said symbol (n) to generate a filtered symbol (n), said symbol (n) being one of said plurality of discrete binary symbols;

differentially detecting said filtered symbol;

determining a first phase ⊖

(n) of said filtered symbol (n) by a phase slicer;

determining a second phase ⊖

(n) of said filtered symbol (n) by an arc tangent processor; and

determining the phase error signal;

or

II. correcting the interference between each of said discrete binary symbols for all symbols stored;

outputting each corrected symbol, one at a time;

determining a first phase ⊖

(n) of a symbol (n), said symbol (n) being one of said plurality of discrete binary symbols by a phase slicer;

determining a second phase ⊖

(n) of said symbol (n) by an arc tangent processor; and

determining the phase error signal.