Phase-locked loop timing recovery circuit

• US 5,581,585 A
• Filed: 10/21/1994
• Issued: 12/03/1996
• Est. Priority Date: 10/21/1994
• Status: Expired due to Term

• Current Assignee: Level One Communications, Inc. (Intel Corporation)
• Original Assignee: Level One Communications, Inc. (Intel Corporation)
• Inventors: Everitt, James W., Buttle, Kenneth G., Takatori, Hiroshi, Ray, Daniel L.
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): ESPOSO, HUONG L
• Application Number:
  US08/327,184
• Time in Patent Office: 774 Days
• Field of Search: 375/355, 375/233, 375/232, 375/229, 375/230, 375/235, 375/327, 375/328, 375/293, 375/294, 375/346, 375/348, 375/350, 331/376, 331/1 A, 455/255, 455/257-260, 364/724.19, 364/724.2, 333/18, 333/28 R, 327/141, 327/155, 327/156, 327/159, 327/162, 327/163, 370/100.1
• US Class Current: 375/376
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 7/0058 detection of error based on equalizer tap values
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

A timing recovery apparatus for recovering the timing from sparse timing information in multi-level or partial response codes. The timing recovery apparatus includes a switch for sampling an incoming line code signal according to a selectable sample rate, a feed forward equalizer for filtering the sampled signal, a decision feedback equalizer for cancelling intersymbol interference in the filtered signal and for recovering the timing in the sampled signal. The timing recovery circuit creates a phase correction signal in response to a signal received from the feed forward equalizer and thereby control the sample rate of the sample switch so that the signal-to-noise ratio at the node before the decision is maximized. The voltage controlled crystal oscillator may be controlled within a certain frequency range by using a second phase detector which compares the phase of the signal controlling the sampling of the incoming line code with a reference clock.

Claims

1. A timing recovery circuit, comprising:

sampling means for sampling an incoming line code signal according to a selectable sample rate;

a feed forward equalizer, coupled to the sampling means, comprises a transversal filter for receiving and filtering the sampled incoming line code signal, the transversal filter comprising N taps, each of the N taps providing an output, N-1 multipliers for multiplying each of the outputs of N-1 of the N taps by a respective coefficient factor, each of the N-1 multipliers providing an output, and an adder for adding the respective outputs of the N-1 multipliers and the output of the Nth tap to produce a filtered signal that is adapted to the sampled incoming line code signal;

a decision feedback equalizer, coupled to the feed forward equalizer, for cancelling an intersymbol interference in the filtered signal, for adjusting the filtering in the feed forward equalizer, and for recovering timing information from the filtered signal;

phase determining means, coupled to a multiplier in the feed forward equalizer, the phase determining means receiving a coefficient factor from the multiplier and creating a phase correction signal in response thereto;

sample control means, coupled to the phase determining means and the sampling means, for creating a sample control signal for selecting the sample rate of the sampling means in response to the phase correction signal generated by the phase determining means.

2. The timing recovery apparatus of claim 1, wherein the decision feedback equalizer further comprises decision feedback means for estimating intersymbol interference, accumulating means for receiving the filtered signal of the feed forward equalizer and the estimated intersymbol interference from the decision feedback means, and decision means for receiving the output of the accumulating means and for generating the recovered timing information.

3. The timing recovery apparatus of claim 1, wherein the phase determining means further comprises a comparator for comparing a threshold level to the coefficient factor received from the feed forward equalizer and a loop filter, coupled to the output of the comparator, for generating the phase correction signal in response thereto.

4. The timing recovery apparatus of claim 3, wherein the threshold level is a predetermined constant threshold level.

5. The timing recovery apparatus of claim 3, wherein the threshold level is generated by the decision feedback equalizer.

6. The timing recovery apparatus of claim 1, wherein the sample control means is a voltage controlled crystal oscillator.

7. A timing recovery circuit, comprising:

sampling means for sampling an incoming line code signal according to a selectable sample rate;

a transversal filter means, coupled to the sampling means, for filtering the sampled signal, said transversal filter means having N delay taps, each of the taps providing an output, the transversal filter means further comprising N-1 coefficient means, each coupled to one of N-1 of the N taps, for multiplying the respective output of the N-1 taps by a respective coefficient factor, and an adder for adding the outputs of the N-1 coefficient means to the output of the Nth tap;

decision feedback equalizer means, coupled to the transversal filter means, for estimating intersymbol interference in the output of the transversal filter means and for generating an error signal fed back to the transversal filter means;

accumulating means for receiving the output of the transversal filter means and the estimated intersymbol interference from the decision feedback equalizer means, for accumulating the estimated symbol interference and the output of the transversal filter means, and for generating an output in response thereto;

decision means, coupled to the accumulating means, for receiving the output of the accumulating means and for recovering timing information from the sampled signal;

phase determining means, coupled to the transversal filter means, for comparing a coefficient value for the (N-1)th tap to a threshold level and for generating a phase correction signal in response thereto; and

sample control means, coupled to the phase determining means and the sampling means, for creating a sample control signal for selecting the sample rate of the sample means in response to the phase correction signal.

8. The timing recovery apparatus of claim 7, wherein the threshold level is a predetermined constant threshold level.

9. The timing recovery apparatus of claim 7, wherein the threshold level is generated in response to the error signal from the error decision feedback equalizer means.

10. The timing recovery apparatus of claim 7, wherein the sample control means is a voltage controlled crystal oscillator.

11. A timing recovery circuit, comprising:

first sampling means for sampling an incoming line code signal according to a first sample rate;

a feed forward equalizer, coupled to the first sampling means, the feed forward equalizer further comprising a transversal filter means for receiving and filtering the sampled incoming line code signal, the transversal filter means having N taps, each of the N taps providing an output, N-1 coefficient means for multiplying the outputs of N-1 of the N taps by a respective coefficient factor, and an adder for adding the outputs of the N-1 coefficient means and the output of the Nth tap to produce a filtered signal that is adapted to the sampled incoming line code signal;

a decision feedback equalizer, coupled to the feed forward equalizer, for cancelling intersymbol interference in the filtered signal, for recovering timing information from the sampled signal, and for generating an error signal in response thereto for adjusting the filtered signal in the feed forward equalizer;

phase determining means, coupled to the decision feedback equalizer, for creating a phase correction signal in response to the recovered timing information and the error signal; and

sample control means, coupled to the phase determining means and the first sampling means, for creating a sample control signal for selecting a new sample rate for the sample means in response to the phase correction signal generated by the phase determining means.

12. The timing recovery apparatus of claim 11, further comprising means, coupled to the feed forward equalizer and the phase determining means, for automatically calculating a threshold level resulting in the highest signal-to-noise ratio at the input of the decision feedback equalizer.

13. The timing recovery apparatus of claim 11, wherein the feed forward equalizer further comprises a transversal filter means having N taps, each of the N taps providing an output, a first coefficient factor control means, coupled to N-2 of the N taps, for modifying a coefficient factor to the N-2 taps in response to the error signal, a second coefficient factor control means, coupled to the (N-1)th tap, for modifying a coefficient factor to the (N-1)th tap in response to the error signal, and an adder for adding the output of the Nth tap to the outputs of the first and second coefficient factor control means.

14. The timing recovery apparatus of claim 11, wherein the phase determining means further comprises a loop filter, automatic threshold calculation means, coupled to the error decision feedback equalizer, for generating a threshold level signal in response to the error signal, and comparator means, coupled to the loop filter and the threshold calculation means, for generating a signal in response to the threshold level signal and the coefficient factor value from the (N-1)th tap.

15. The timing recovery apparatus of claim 11 wherein the phase determining means further comprises:

a multiplier, coupled to the decision feedback equalizer, for generating a pulse train in response to the error signal and the recovered timing signals;

second sampling means, coupled to the multiplier for sampling the pulse train, the second sampling means sampling the incoming signal according to a second selectable sample rate;

a loop filter, coupled to the second sampling means, for providing a voltage output;

a second sample control means, coupled to the loop filter, for creating a sampling control signal for regulating the first sample rate of the first sampling means in response to the voltage output of the loop filter; and

phase comparison means, coupled to the output of the second sample control means and to a reference clock, for comparing the phase of the sampling control signal to the phase of the reference clock, the phase comparison means generating a sampling control signal for regulating the second sample rate of the second sampling means in response thereto.