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Phase-locked loop timing recovery circuit

  • US 5,581,585 A
  • Filed: 10/21/1994
  • Issued: 12/03/1996
  • Est. Priority Date: 10/21/1994
  • Status: Expired due to Term
First Claim
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1. A timing recovery circuit, comprising:

  • sampling means for sampling an incoming line code signal according to a selectable sample rate;

    a feed forward equalizer, coupled to the sampling means, comprises a transversal filter for receiving and filtering the sampled incoming line code signal, the transversal filter comprising N taps, each of the N taps providing an output, N-1 multipliers for multiplying each of the outputs of N-1 of the N taps by a respective coefficient factor, each of the N-1 multipliers providing an output, and an adder for adding the respective outputs of the N-1 multipliers and the output of the Nth tap to produce a filtered signal that is adapted to the sampled incoming line code signal;

    a decision feedback equalizer, coupled to the feed forward equalizer, for cancelling an intersymbol interference in the filtered signal, for adjusting the filtering in the feed forward equalizer, and for recovering timing information from the filtered signal;

    phase determining means, coupled to a multiplier in the feed forward equalizer, the phase determining means receiving a coefficient factor from the multiplier and creating a phase correction signal in response thereto;

    sample control means, coupled to the phase determining means and the sampling means, for creating a sample control signal for selecting the sample rate of the sampling means in response to the phase correction signal generated by the phase determining means.

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