Condition detector and prioritizer with associativity determination logic

• US 5,581,730 A
• Filed: 07/06/1994
• Issued: 12/03/1996
• Est. Priority Date: 07/06/1994
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Silla, Mark
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US08/271,373
• Time in Patent Office: 881 Days
• Field of Search: 395/471, 395/483, 395/481
• US Class Current: 711/144
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/125 being generated by decoding an array or storage

Abstract

A device for simultaneously detecting more than one condition, where each condition corresponds to a specific memory cell of an array of more than one memory cell, each specific memory cell of the array having a distinct index given by a first number of bits and a distinct associativity given by a second number of bits, each condition triggers a particular, distinct task, and each task, if more than one, is prioritized.

Claims

1. A device for simultaneously detecting more than one condition, each said condition corresponding to a specific memory cell of an array of more than one memory cell, each said specific memory cell of said array having a distinct index given by a first number of bits and a distinct associativity given by a second number of bits, each said condition triggering a particular, distinct task, and prioritizing each said task, if more than one, comprising:

more than one input signal, each said input signal being relative to and indicative of said condition for one said specific memory cell;

circuitry for simultaneously receiving each said more than one input signal and logically determining said distinct associativity and said distinct index for each said specific memory cell and prioritizing each said task dictated by each said condition indicated by each said input with respect to each other said task dictated by each other said condition indicated by each other said input; and

output signals for sequentially outputting each said distinct associativity and said distinct index for each specific memory cell in the order of prioritization of each said task.

2. The device of claim 1, wherein said circuitry comprises:

first NOR gate, said first NOR gate receiving each said more than one input signals and outputting as a first gate output signal any of said input signals indicative that said condition is modified condition;

second NOR gate, said second NOR gate receiving an enable signal and said first gate output signal from said first NOR gate, if any, said second NOR gate outputting an index enable signal of enable if said enable signal or said first gate output signal indicates that said condition is modified condition;

index transistors, each having a first gate, a first drain and a first source, said index transistors corresponding in number to each of said first number of bits, said index transistors being commonly electrically connected by said first gate of each of said index transistors and being commonly electrically connected by said first drain of each of said index transistors, each said first gate of each of said index transistors being electrically connected with said index enable signal, said index transistors being enabled if said index enable signal indicates that said condition is modified condition;

associativity transistors, each having a second gate, a second drain and a second source, said associativity transistors corresponding in number to each of said second number of bits, said associativity transistors being commonly electrically connected by said second gate of each of said associativity transistors and being commonly electrically connected by said second drain of each of said associativity transistors; and

a transistor, having a third gate, a third drain, and a third source, for enabling said associativity transistors if said index transistors are enabled, said transistor being electrically connected by said third gate with said index enable signal and by said third drain with each said first drain of said index transistors;

wherein each said first source of said index transistors outputs bits as said output signals indicative of said distinct index if said index transistors are enabled and each said second source of said associativity transistors outputs bits as said output signal indicative of said distinct associativity if said index transistors and said associativity transistors, via said transistor, are each enabled.

3. The device of claim 1, wherein the device is employed with a cache memory of a digital computer to speed external memory write procedures.

4. A method for simultaneously detecting more than one condition, each said condition corresponding to a specific memory cell of an array of more than one memory cell, each said specific memory cell of said array having a distinct index given by a first number of bits and a distinct associativity given by a second number of bits, each said condition triggering a particular, distinct task, and prioritizing each said task, if more than one, comprising the steps of:

inputting more than one input signal, each said input signal being relative to and indicative of said condition for one said specific memory cell;

simultaneously receiving each said more than one input signal;

logically determining said distinct associativity and said distinct index for each said specific memory cell;

prioritizing each said task dictated by each said condition indicated by each said input with respect to each other said task dictated by each other said condition indicated by each other said input; and

sequentially outputting each said distinct associativity and said distinct index for each specific memory cell in the order of prioritization of each said task.

5. The method of claim 4, wherein said step of receiving includes the steps of:

receiving each said more than one input signals;

wherein said step of logically determining includes the steps of;

outputting as a first gate output signal any of said input signals indicative that said condition is modified condition;

receiving an enable signal and said first gate output signal, if any;

outputting an index enable signal of enable if said enable signal or said first gate output signal indicates that said condition is modified condition; and

wherein said step of prioritizing includes the steps of;

enabling index transistors, each having a first gate, a first drain and a first source, said index transistors corresponding in number to each of said first number of bits, said index transistors being commonly electrically connected by said first gate of each of said index transistors and being commonly electrically connected by said first drain of each of said index transistors, each said first gate of each of said index transistors being electrically connected with said index enable signal, said index transistors being enabled if said index enable signal indicates that said condition is modified condition;

enabling associativity transistors, each having a second gate, a second drain and a second source, said associativity transistors corresponding in number to each of said second number of bits, said associativity transistors being commonly electrically connected by said second gate of each of said associativity transistors and being commonly electrically connected by said second drain of each of said associativity transistors;

enabling a transistor, having a third gate, a third drain, and a third source, if said index transistors are enabled by said step of enabling said index transistors, said transistor being electrically connected by said third gate with said index enable signal and by said third drain with each said first drain of said index transistors;

outputting as said output signals bits indicative of said distinct index if said index transistors are enabled by said step of enabling said index transistors; and

outputting bits as said output signal indicative of said distinct associativity if said index transistors and said associativity transistors, via said transistor, are each enabled.

6. The method of claim 4, wherein said method is employed with a cache memory of a digital computer to speed external memory write procedures.

7. An encoder, comprising:

level one logic block, said level one logic block simultaneously receiving inputs indicative of locations and conditions of each of a number of observed memory cells, said conditions for each of said number of observed memory cells being either modified or unmodified;

level two logic block, said level two logic block receiving enabling output signals of said level one logic block, said enabling output signals indicative of any of said inputs to said level one logic block indicating a modified condition, said enabling output signals serving to enable said level two logic block; and

level three logic block, said level three logic block being enabled by receipt of an enabling signal output by said level two logic block when said level two logic block is enabled;

wherein said encoder, for each of said inputs indicative of said modified condition, outputs a distinct index address and a distinct associativity address, said outputs being prioritized.

8. A method for determining an index address and an associativity address of a modified memory cell in a cache memory of a digital computer, comprising the steps of:

observing simultaneously several of said memory cells;

detecting whether any of said memory cells are modified;

outputting said index address and said associativity address corresponding to each of said memory cells that is modified; and

prioritizing said steps of outputting, if more than one, so that only a single one of said index address and said associativity address corresponding to said modified memory cell is output at any time.

9. A device for determining an index address and an associativity address of a modified memory cell in a cache memory of a digital computer, comprising:

circuitry for observing simultaneously several of said memory cells;

circuitry for detecting whether any of said memory cells are modified;

circuitry for outputting said index address and said associativity address corresponding to each of said memory cells that is modified; and

circuitry for prioritizing said steps of outputting, if more than one, so that only a single one of said index address and said associativity address corresponding to said modified memory cell is output at any time.

10. A method for determining an index and an associativity of a modified memory cell of an array of memory cells, comprising the steps of:

simultaneously monitoring several of said memory cells and detecting signals indicative of a modified or unmodified status of each of several memory cells of said array of memory cells;

determining whether any of said signals detected indicates one or more of said several memory cells is modified;

determining an index of each of said modified memory cells;

determining an associativity of each of said modified memory cells;

logically choosing any of said signals indicative of said one or more of said modified memory cells for each of said determining steps; and

logically enabling any of said signals indicative of said one or more of said modified memory cells for each of said determining steps.

11. A device for determining an index and an associativity of a modified memory cell of an array of memory cells, comprising:

circuitry for simultaneously monitoring several of said memory cells and for detecting signals indicative of a modified or unmodified status of each of several memory cells of said array of memory cells;

circuitry for determining whether any of said signals detected indicates one or more of said several memory cells is modified;

circuitry for determining an index of each of said modified memory cells;

circuitry for determining an associativity of each of said modified memory cells;

circuitry for logically choosing any of said signals indicative of said one or more of said modified memory cells for each of said determining steps; and

circuitry for logically enabling any of said signals indicative of said one or more of said modified memory cells for each of said determining steps.