Two lane computing systems

• US 5,581,739 A
• Filed: 07/26/1994
• Issued: 12/03/1996
• Est. Priority Date: 10/10/1991
• Status: Expired due to Fees

• Current Assignee: Smiths Industries Public Limited Company
• Original Assignee: Smiths Industries Public Limited Company
• Inventors: FitzPatrick, Roger S.
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/280,511
• Time in Patent Office: 861 Days
• Field of Search: 395/800, 395/500, 395/182.02, 395/182.12, 395/182.11, 395/185.17, 395/183.02, 395/183.09, 395/183.08, 395/183.01, 364/DIG. 1, 364/DIG. 2, 364/489, 364/578, 364/580, 371/22.4, 371/27, 371/500
• US Class Current: 703/13
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/165 with continued operation after detection of the error
• CPC Class Codes: G06F 11/184 where the redundant components implement processing functionality
• CPC Class Codes: G06F 11/2023 Failover techniques

Abstract

A dual lane computing system has at least one processor in each lane, each processor having an associated store which stores input data supplied to the processor and their time of arrival. The lanes produce nominally-identical outputs which are supplied to a comparator that detects when there is a discrepancy between the lanes. When a discrepancy is detected, an external processor is loaded with software that simulates the operation of the lanes. The data in the store associated with one of the lane processors is supplied to the simulator processor in respect of the input just prior to the detection of the discrepancy. The simulator simulates the operation of one lane utilizing this data and its output is compared in the comparator with the actual output of that lane as recorded when the discrepancy occurred.

Claims

1. A computing system comprising:

two lanes, each lane having at least one processing means, the lanes being arranged to produce respective, nominally-identical outputs;

means for supplying input data to each lane;

means for detecting a discrepancy between said outputs and signalling a fault;

store means associated with each said processing means, said store means being arranged to store input data supplied to its respective processing means and to re-inject input data to its respective processing means if the system should be restarted following an interruption to the system;

simulator means for simulating operation of said processing means of one of the lanes on detection of a discrepancy between the outputs from said lanes;

means for supplying the simulator means with said input data stored in said store means of one of the lanes which was supplied to its associated processing means just prior to the detection of a discrepancy, said simulator means being arranged to simulate the operation of the processing means of said one lane utilizing the data from said store means supplied to the store means just prior to detection of the discrepancy; and

means for comparing an output of the simulator means with the outputs of the lanes produced on detection of the discrepancy so as thereby to identify which of said lanes is a malfunctioning lane.

4. A computing system according to claim 1, wherein the simulator means is also arranged to simulate operation of the second of the processing means.

5. A computing system according to claim 4, wherein the simulator means is arranged to perform two simulations of the second processing means one of which utilizes the output from the first processing means and the other of which utilizes the output produced by simulation of the first processing means.

2. A computing system comprising:

two lanes, each lane having at least one processing means, the lanes being arranged to produce respective, nominally-identical outputs;

means for supplying input data to each lane;

means for detecting a discrepancy between said outputs and signalling a fault;

store means associated with each said processing means, said store means being arranged to store input data supplied to its respective processing means;

simulator means for simulating operation of said processing means of one of the lanes on detection of a discrepancy between the outputs from said lanes;

means for supplying the simulator means with said input data stored in said store means of one of the lanes which was supplied to its associated processing means just prior to the detection of a discrepancy, said simulator means being arranged to simulate the operation of the processing means of said one lane utilizing the data from said store means supplied to the store means just prior to detection of the discrepancy;

means for comparing an output of the simulator means with the outputs of the lanes produced on detection of the discrepancy so as thereby to identify which of said lanes is a malfunctioning lane;

a software store of software simulating the operation of the lanes, the software store being separate from the simulator means, and means for loading the contents of the software store into the simulator means only on detection of a discrepancy between the two lane outputs.

3. A computing system comprising:

two lanes, each lane having at least two processing means, the lanes being arranged to produce respective, nominally-identical outputs;

means for supplying input data to each lane;

means for detecting a discrepancy between said outputs and signalling a fault;

store means associated respectively with each said processing means, each of said store means being arranged to store input data supplied to its respective processing means;

simulator means for simulating operation of said processing means of one of the lanes on detection of a discrepancy between the outputs from said lanes;

means for supplying the simulator means with said input data stored in said store means of one of the lanes which was supplied to its associated processing means just prior to the detection of a discrepancy, said simulator means being arranged to simulate the operation of the processing means of said one lane utilizing the data from said store means supplied to the store means just prior to detection of the discrepancy; and

means for comparing an output of the simulator means with the outputs of the lanes produced on detection of the discrepancy so as thereby to identify which of said lanes is a malfunctioning lane;

the simulator means being operative to simulate operation of a first of the processing means in a lane and supply an output to a second of the processing means in that lane instead of the output from said first processing means on detection of a fault in the first processing means.