Data feeder control system for performing data integrity check while transferring predetermined number of blocks with variable bytes through a selected one of many channels

• US 5,581,790 A
• Filed: 06/07/1994
• Issued: 12/03/1996
• Est. Priority Date: 06/07/1994
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Sefidvash, Khorvash
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Chen, Duo
• Application Number:
  US08/253,436
• Time in Patent Office: 910 Days
• Field of Search: 395/854, 395/853, 395/280, 395/842, 395/824, 395/838, 371/57.1
• US Class Current: 710/34
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

Multiple numbers of "sets" of sender-receiver units operate concurrently to transfer blocks of data. The number of blocks to be transferred in each set is predetermined by a main host computer which registers the number-of-blocks-to-be-transferred into a protocol-controller in each set of sender-receiver units. An associated data feeder control system monitors the number of data blocks residing in a buffer memory, which has dedicated storage for each sender-receiver unit, and will only permit data block transfer to receiver units only to the amount presently available in the buffer memory until, eventually, the predetermined number of data blocks, for each set, is transferred to completion.

Claims

1. A data feeder and management system using a processor-controller means for controlling data transfers between a plurality of main host computers and a plurality of peripheral devices, said data composed of "B" blocks of "d" bytes which include an original error detection code (EDC) signature for each block, said system comprising:

(a) a memory buffer means for holding blocks of data being transferred between a main host computer and a specified peripheral device, said buffer means connected to said main host computers and including (i) dedicated segments for holding data being transferred to/from N peripheral devices on N channel bus means where each segment includes ID means for recording the amount "B" of data blocks to be transferred on each one of said N channel bus means; and

(ii) means to transfer said data block amount of "d" bytes to an associated protocol controller means;

(b) a plurality N of said protocol controller means, each protocol controller means having a channel bus means connected to said memory buffer means via a selecting multiplexer means, each said protocol controller means connecting to a peripheral device which can receive or send data;

(c) said processor-controller means for tracking the number of data blocks transferred on each one of said N channel bus means, said processor-controller means including channel bus arbitration means for enabling said selecting multiplexer means to select one of said channel bus means for data transfer;

(d) a plurality of N Data Feeder Control means, each Feeder Control means attached to an associated channel bus means and including;

(d1) counter means for registering when the number of data blocks transferred has reached the amount of "B";

(d2) interrupt means to remote accessibility to the associated channel bus means which has successfully transferred "B" blocks of data by signalling said processor-controller means;

(e) a plurality of N integrity checking circuit means, operating directly on-the-fly during data transfers on said channel bus means, each said integrity circuit means attached to one of said channel bus means and including;

(e1) means to parity check each byte of data transferred;

(e2) means to generate a resultant error detection code (EDC) signature for each block of data transferred;

(e3) means to compare said original EDC signature with said resultant EDC signature, and to generate an error signal if a mismatch occurs.

2. The system of claim 1 wherein each of said protocol-controller means includes means to receive a command from said main host computer to transfer "B" blocks of data and store said number "B" until "B" blocks have been transferred.

3. The system of claim 2 wherein said processor-controller means includes:

(a) means to inhibit said counter means so as to transfer only the number, "R", of data blocks presently residing in said memory buffer means where "R" represents the number of uncompleted blocks needed to complete the full transfer of "B" blocks.

4. The system of claim 3 wherein said processor controller means includes:

(a) means to remove accessibility to a channel bus means when said memory buffer means has no stored data blocks destined for that channel bus means.

5. The system of claim 1 wherein each of said protocol controller means includes:

(a) means to disable said integrity checking circuit means when data blocks without original error detection codes (EDC) are being transmitted.

6. A data feeder control and management system for the monitoring and supervision of multiple numbers of sender-receiver modules wherein a sender module transmits data organized in "B" blocks having "d" bytes including a header indicating the number "d" of bytes in each block and an original error detection code (EDC) for each block, each set of sender-receiver modules connected by a channel bus means, said system comprising:

(a) a multiple number of N sets of sender-receiver modules, each set connected by its own channel bus means;

(b) N integrity checking means operating on-the-fly for checking the parity of each byte of each word transferred on each of said N channel bus means and for checking the original error detection code (EDC) signature of each block transferred on each of said channel bus means, said checking means including;

(b1) means to generate a resultant EDC for each block transferred for comparison with said original EDC block;

(b2) means to signal an error signal to said processor-controller means when said EDC codes do not match.

(c) processor controller means connected to each of said channel bus means for regulating data transfers on each channel bus means, including;

(c1) means to select any one of said multiple sets of sender-receiver units to set the prescribed amount of data to be transferred and to signal said processor-controller means when the prescribed amount of data has been transferred;

(d) N data feeder control means, each means including;

counter controller means to register the amount of data transferred on each one of said sets of sender-receiver modules and to notify said processor-controller means when the prescribed amount of data has been transferred;

(e) means to interrupt and inform said processor-controller means when said prescribed amount of data transfer has been completed.