Method for manufacturing field effect controlled semiconductor components

• US 5,583,060 A
• Filed: 11/03/1995
• Issued: 12/10/1996
• Est. Priority Date: 11/04/1994
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Hertrich, Helmut, Strack, Helmut, Tihanyi, Jenoe
• Primary Examiner(s): Quach, T. N.
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/552,702
• Time in Patent Office: 403 Days
• Field of Search: 437/31, 437/29, 437/40 DM, 437/41 DM, 437/913, 437/203, 437/26, 148/DIG. 126
• US Class Current: 438/138
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

The base zones of MOSFETs and IGBTs are generated by implanting dopants of the second conductivity type into the surface of a first layer of the first conductivity type, and a second layer of the first conductivity type is deposited thereon. During the deposition, the dopants diffuse up to the surface of the second layer and form base zones. The base zones are thereby provided with a laterally expanded region of high conductivity under the surface through which the minority carriers can flow off to the source electrode with low voltage drop.

Claims

1. Method for manufacturing a field effect controlled semiconductor component, comprising the steps of:

providing a first layer of a first conductivity type on a substrate, the first layer having a surface;

generating zones of a second conductivity type in the surface of the first layer by implantation of dopants, the zones of the second conductivity type having lateral dimensions;

epitaxially depositing a second layer of the first conductivity type on the first layer and the zones of the second conductivity type upon all around diffusion of dopants out of the zones of the second conductivity type thereby generating base zones, the second layer having a surface;

generating source zones in the surface of the second layer over the base zones such that the lateral dimensions of the zones of the second conductivity type are at least congruent with the source zones;

generating via openings that extend to the dopant maximum of the base zones in the source zones and base zones; and

electrically connecting the source zones and the base zones to one another by a metal layer extending into the via openings.

2. Method according to claim 1, wherein following the epitaxial deposition of the second layer, the method further comprises the step of:

exposing the semiconductor component to a higher temperature than the temperature at which the second layer was epitaxially deposited.

3. Method according to claim 1, wherein the step of generating source zones in the second layer at the surface of the semiconductor body is further defined by generating the source zones by implantation of dopants.

4. Method according to claim 1, further comprising the step of:

implanting dopants surface-wide into the surface of the semiconductor body after the epitaxial deposition of the second layer and the production of the source zones and base zones.

5. Method according to claim 1, wherein the base zones and the source zones are generated cell-like.

6. Method for manufacturing a field effect controlled semiconductor component, comprising the steps of:

providing a first layer on a substrate of a semiconductor body, the first layer having a surface;

generating a zone of a second conductivity type in the surface of the first layer by implantation of dopants;

generating trenches in the surface of the first layer, wherein the trenches are constructed and arranged to accept vertical gate electrodes thereby producing a plurality of base zones of the second conductivity type;

epitaxially depositing a second layer of the first conductivity type on the zones of the second conductivity type and at the walls of the trenches upon all around diffusion of dopants out of the zones of the second conductivity type thereby generating base zones;

providing the base zones of the second conductivity type with such dimensions that their dopants in the trenches extend up to the surface of the second layer;

generating source zones in the second layer at the surface of the semiconductor body;

generating via openings that extend up to the dopant maximum of the zones of the second conductivity type in the source zones and in the second layer at the surface of the semiconductor body; and

electrically connecting the source zones and the base zones of the second conductivity type to one another by a metal layer extending into the via openings.

7. Method according to claim 6, wherein the step of generating source zones in the second layer at the surface of the semiconductor body is further defined by generating the source zones by implantation of dopants.

8. Method according to claim 6, further comprising the step of:

implanting dopants surface-wide into the surface of the semiconductor body after the epitaxial deposition of the second layer and the production of the source zones and base zones.

9. Method according to claim 6, wherein the base zones and the source zones are generated cell-like.

10. Method according to claim 6, following the epitaxial deposition of the second layer, exposing the semiconductor component to a higher temperature than the temperature at which the second layer was epitaxially deposited.