Method of making a MOS semiconductor device

• US 5,583,065 A
• Filed: 12/06/1995
• Issued: 12/10/1996
• Est. Priority Date: 11/23/1994
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Miwa, Hiroyuki
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US08/568,407
• Time in Patent Office: 370 Days
• Field of Search: 437/40 RG, 437/41 RG, 437/44, 437/203, 437/228 ES, 437/228 POL, 257/330
• US Class Current: 438/304
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A method of making a semiconductor device wherein fluctuations of an effective length of the conduction area and placement thereof relative to source and drain regions is controlled during manufacture. A first insulation film is formed on a semiconductor substrate. A first thin film is formed on the first insulation film. A trench is formed below a surface of the substrate by etching said first thin film, first insulation film, and semiconductor substrate. A second insulation film is formed along an inside wall of the trench. A first electrically conductive film is formed along an inside wall of the second insulation film within the trench and an embedded electrode is formed within a space defined by said first electrically conductive film. The first thin film is removed and then impurities are introduced into the substrate using the first electrically conductive film as a mask so as to form source and drain with the gate trench being automatically centered between the source and drain region, and a fluctuation of an effective length of a conduction region is avoided.

Claims

1. A method of making a semiconductor device, comprising the steps of:

providing a semiconductor substrate;

forming a first insulation film on said semiconductor substrate along with insulating separating elements which are thicker than a thickness of said first insulation film;

forming a first film on said first insulation film, said first film having an etching resistance which is different than said first insulation film;

successively etching the first film, first insulation film, and the substrate to form a trench in the substrate, said trench having inside walls and a floor;

forming a second insulation film along said inside walls and floor of said trench, said second insulation film having inside walls and a floor;

forming a first electrically conductive film along said inside walls and floor of said second insulation film within said trench, said first electrically conductive film having inside walls and a floor;

filling in a space defined by said inside walls and floor of said first electrically conductive film in said trench with an electrically conductive material serving as an embedded gate electrode in said trench;

removing portions of the first electrically conductive film and embedded gate electrode protruding above the trench and above the first film by chemical mechanical polishing using the first film as an etching stopper;

removing the first film from above the first insulation film and around upper portions of said first electrically conductive film and embedded electrode which project above the first insulation film;

after removing said first thin film, forming a second electrically conductive film on the first insulation film and then conducting an etching of the second electrically conductive film so as to form respective side walls directly abutting and alongside opposite portions of the first electrically conducting film extending above said first insulation film, and selecting a thickness of said side walls for defining a distance between said shallow trench and said source and drain zones to be later provided in said substrate, edges of the source and drain zones adjacent the trench being spaced outwardly from said inside walls of said trench; and

introducing impurities into said semiconductor substrate between said insulating separating elements and said trench using said embedded gate electrode and said first and second electrically conductive films as a mask to form respective source and drain zones.

2. A method of making a semiconductor device according to claim 1 wherein said second insulation film is formed by rapid thermal oxidation.

3. A method of making a semiconductor device according to claim 1 including the step of forming said source and drain zones by ion-implantation.

4. A method of making a semiconductor device according to claim 1 wherein said first insulation film comprises a gate oxide film and said first film on said first insulation film comprises a silicon nitride film.

5. A method of making a semiconductor device according to claim 1 wherein the insulating separating elements have a thickness in a range of 400-500 nm and said first insulation film and said second insulation film have a thickness in a range of 10-20 nm.

6. A method of making a semiconductor device according to claim 1 including the step of providing said first electrically conductive film as a polysilicon film.

7. A method of making a semiconductor device according to claim 1 including the step of providing said electrically conductive material serving as an embedded gate electrode as a tungsten silicon film introduced with a CVD method.

8. A method of making a semiconductor device according to claim 1 including the step of providing said second electrically conductive film as a polysilicon film and forming said side walls by anisotropic etching.

9. A method of making a semiconductor device according to claim 1 including the step forming said source and drain zones by ion injection followed by a thermal processing activation.