Semiconductor memory device having stacked capacitors

• US 5,583,358 A
• Filed: 10/17/1994
• Issued: 12/10/1996
• Est. Priority Date: 01/08/1988
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawamoto, Yoshifumi, Kimura, Shinichiro, Sakai, Yoshio, Hashimoto, Naotaka, Takeda, Eiji, Kure, Tokuo, Kaga, Toru
• Primary Examiner(s): Limanek, Robert P.
• Application Number:
  US08/324,352
• Time in Patent Office: 785 Days
• Field of Search: 257/306
• US Class Current: 257/306
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments

Abstract

A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

Claims

1. A semiconductor memory device having a plurality of word lines formed by a first level wiring layer covering a surface of a semiconductor substrate, a plurality of bit lines formed by a second level wiring layer covering said first level wiring layer and a plurality of dynamic memory cells whose storage electrodes of capacitors are formed by a third level wiring layer coveting said second level wiring layer, comprising:

first, second, third and fourth word lines of said plurality of word lines, which are successively disposed;

first, second and third bit lines of said plurality of bit lines, which are successively disposed;

a first dynamic memory cell of said plurality of dynamic memory cells, of which a storage electrode of a capacitor is coupled to a source or a drain of a MOS transistor of said first dynamic memory cell through a first capacitor contact hole;

a second dynamic memory cell of said plurality of dynamic memory cells, of which a storage electrode of a capacitor is coupled to a source or a drain of a MOS transistor of said second dynamic memory cell through a second capacitor contact hole;

a third dynamic memory cell of said plurality of dynamic memory cells, of which a storage electrode of a capacitor is coupled to a source or a drain of a MOS transistor of said third dynamic memory cell through a third capacitor contact hole; and

,

a fourth dynamic memory cell of said plurality of dynamic memory cells, of which a storage electrode of a capacitor is coupled to a source or a drain of a MOS transistor of said fourth dynamic memory cell through a fourth capacitor contact hole,

wherein said second bit line is coupled to the drains or sources of transistors of two of said first, second, third and fourth dynamic memory cells through a second bit line contact hole which is between said second word line and said third word line;

wherein said first capacitor contact hole is between said first word line and said second word line, and between said first bit line and said second bit line,

wherein said second capacitor contact hole is between said third word line and said fourth word line, and between said first bit line and said second bit line,

wherein said third capacitor contact hole is between said first word line and said second word line, and between said second bit line and said third bit line,

wherein said fourth capacitor contact hole is between said third word line and said fourth word line, and between said second bit line and said third bit line,

wherein said second bit line is disposed in a longitudinal direction over said first, second, third and fourth word lines,

wherein a major portion of the second bit line comprises a straight line portion parallel to the longitudinal direction of said second bit line and said second bit line is coupled to drains or sources of transistors of said third and fourth dynamic memory cells through said second bit line contact hole; and

,

wherein said second bit line contact hole overlaps said straight line portion of said major portion of said second bit line.

2. The semiconductor memory device according to claim 1, further comprising a fifth word line next to said fourth word line,

wherein said second bit line is coupled to drain or source of a transistor of said second dynamic memory cell through an other second bit line contact hole which is between said fourth word line and said fifth word line.

3. The semiconductor memory device according to claim 1, further comprising a fifth word line next to said fourth word line,

wherein said first bit line is coupled to drain or source of a transistor of said second dynamic memory cell through a first bit line contact hole which is between said fourth word line and said fifth word line.

4. A semiconductor memory device having a plurality of word lines formed by a first level wiring layer coveting a surface of a semiconductor substrate, a plurality of bit lines formed by a second level wiring layer coveting said first level wiring layer and a plurality of dynamic memory cells whose storage electrodes of capacitors are formed by a third level wiring layer coveting said second level wiring layer, comprising:

first, second, third and fourth word lines of said plurality of word lines, which are successively disposed;

first, second and third bit lines of said plurality of bit lines, which are successively disposed;

a first dynamic memory cell of said plurality of dynamic memory cells, of which a storage electrode of a capacitor is coupled to a source or a drain of a MOS transistor of said first dynamic memory cell through a first capacitor contact hole;

a second dynamic memory cell of said plurality of dynamic memory cells, of which a storage electrode of a capacitor is coupled to a source or a drain of a MOS transistor of said second dynamic memory cell through a second capacitor contact hole;

a third dynamic memory cell of said plurality of dynamic memory cells, of which a storage electrode of a capacitor is coupled to a source or a drain of a MOS transistor of said third dynamic memory cell through a third capacitor contact hole; and

,

a fourth dynamic memory cell of said plurality of dynamic memory cells, of which a storage electrode of a capacitor is coupled to a source or a drain of a MOS transistor of said fourth dynamic memory cell through fourth capacitor contact hole,

wherein said second bit line is coupled to the drains or sources of transistors of two of said first, second, third and fourth dynamic memory cells through a second bit line contact hole which is between said second word line and said third word line;

wherein said first capacitor contact hole is between said first word line and said second word line, and between said first bit line and said second bit line,

wherein said second capacitor contact hole is between said third word line and said fourth word line, and between said first bit line and said second bit line,

wherein said third capacitor contact hole is between said first word line and said second word line, and between said second bit line and said third bit line,

wherein said fourth capacitor contact hole is between said third word line and said fourth word line, and between said second bit line and said third bit line,

wherein said second bit line is disposed in a longitudinal direction over said first, second, third and fourth word lines,

wherein a major portion of the second bit line comprises a straight line portion parallel to the longitudinal direction of said second bit line, and a minor portion of the second bit line comprises a projection portion extending perpendicular to the major portion; and

,

wherein said second bit line contact hole overlaps said straight line portion of said major portion of said second bit line and is coupled to drains or sources of transistors of said third and fourth dynamic memory cells through said second bit line contact hole.

5. The semiconductor memory device according to claim 4, further comprising a fifth word line next to said fourth word line,

wherein said second bit line is coupled to a drain or source of a transistor of said second dynamic memory cell through an other second bit line contact hole which is between said fourth word line and said fifth word line.

6. The semiconductor memory device according to claim 4, further comprising a fifth word line next to said fourth word line,

wherein said first bit line is coupled to a drain or source of a transistor of said second dynamic memory cell through a first bit line contact hole which is between said fourth word line and said fifth word line.

7. The semiconductor memory device according to claim 4, wherein said projection extends in a first direction towards the first bit line.

8. The semiconductor memory device according to claim 4, wherein said projection extends in a second direction towards the third bit line.

9. The semiconductor memory device according to claim 4, wherein said projection extends in a first direction towards the first bit line and in a second direction towards the third bit line.

10. The semiconductor memory device according to claim 4, wherein said second bit line contact hole has an extent in a direction perpendicular to the longitudinal direction of the second bit line substantially equivalent to the major portion of the bit line.

11. The semiconductor memory device according to claim 4, wherein said second bit line contact hole has a dimension sized to completely overlap the major portion of the second bit line in a direction perpendicular to the longitudinal direction of the second bit line.

12. In a memory cell device comprising active regions where channel regions and impurity diffusion layers are formed on a semiconductor substrate to constitute transistors, wherein word lines serve as gate electrodes and bit lines are substantially orthogonal to the word lines and have bit line contact holes through which the bit lines come into contact with the impurity diffusion layers formed on the substrate, conductive layers for connecting the bit lines with the impurity diffusion layers, and electrode contact holes for connecting charge storage electrodes to the substrate, the improvement comprising:

a plurality of memory cells, each having an electrode contact hole associated respectively with a charge storage electrode, wherein each charge storage electrode is bounded on opposite sides by two of the bit lines and two of the word lines and wherein the bit line contact holes substantially overlap the bit lines and are bounded by two of the word lines, and a selected two of the memory cells are disposed between an adjacent two of the bit lines; and

,

wherein a one of the adjacent two of the bit lines is coupled to drains or sources of the electrode contact holes for the selected two of the memory cells.