Stacked devices

• US 5,583,368 A
• Filed: 08/11/1994
• Issued: 12/10/1996
• Est. Priority Date: 08/11/1994
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kenney, Donald M.
• Primary Examiner(s): Wojciechowicz, Edward
• Application Number:
  US08/289,069
• Time in Patent Office: 852 Days
• Field of Search: 257/67, 257/302, 257/330, 257/334, 257/559, 257/514, 257/520, 257/521, 257/513, 257/621, 257/622
• US Class Current: 257/621
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/42304 Base electrodes for bipolar transistors
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

Chips having subsurface structures within or adjacent a horizontal trench in bulk single crystal semiconductor are presented. Structures include three terminal devices, such as FETs and bipolar transistors, rectifying contacts, such as pn diodes and Schottky diodes, capacitors, and contacts to and connectors between devices. FETs have low resistance connectors to diffusions while retaining low overlap capacitance. A low resistance and low capacitance contact to subsurface electrodes is achieved by using highly conductive subsurface connectors which may be isolated by low dielectric insulator. Stacks of devices are formed simultaneously within bulk single crystal semiconductor. A subsurface CMOS invertor is described. A process for forming a horizontal trench exclusively in heavily doped p+ regions is presented in which porous silicon is first formed in the p+ regions and then the porous silicon is etched.

Claims

1. A semiconductor chip, comprising:

a bulk single crystal substrate;

a first horizontal trench buried within said bulk single crystal substrate, said first horizontal trench comprising a surface of bulk single crystal substrate, said trench adjacent one of an undoped region, and a lightly doped region, layer of a first material contacting said surface; and

an electronic device having a first portion adjacent said first horizontal trench, said first portion being within said bulk single crystal substrate, said device further comprising a second portion within said first horizontal trench.

2. A semiconductor chip as recited in claim 1, wherein said first material is a first electrically conductive material forming a contact with said first portion.

3. A semiconductor chip as recited in claim 2, wherein said first electrically conductive material extends through a vertical trench intersecting said first horizontal trench.

4. A semiconductor chip as recited in claim 2, further comprising a second horizontal trench adjacent said portion, wherein said first electrically conductive material extends through said second horizontal trench.

5. A semiconductor chip as recited in claim 2, wherein said first electrically conductive material contacts a surface of said first horizontal trench.

6. A semiconductor chip as recited in claim 5, further comprising a first layer of insulation on said first electrically conductive material.

7. A semiconductor chip as recited in claim 6, wherein said first layer of insulation does not fill said first horizontal trench.

8. A semiconductor chip as recited in claim 2, wherein said contact comprises a Schottky barrier.

9. A semiconductor chip as recited in claim 2, wherein said bulk single crystal semiconductor adjacent said first horizontal trench contains an element diffused from said first electrically conductive material.

10. A semiconductor chip as recited in claim 1, wherein said device is one of a bipolar transistor, an FET, and a diode.

11. A semiconductor chip as recited in claim 1, wherein said portion is a collector of a bipolar transistor.

12. A semiconductor chip as recited in claim 1:

said first material being a second layer of insulation; and

a second electrically conductive material being on said second layer of insulation.

13. A semiconductor chip as recited in claim 12, wherein said second layer of insulation is a gate dielectric and said second layer of electrically conductive material comprises a gate conductor.

14. A semiconductor chip as recited in claim 1, said first material being a second insulator whereby said second insulator provides dielectric isolation for said portion.

15. A semiconductor chip as recited in claim 14, wherein said second insulator does not completely fill said first horizontal trench.

16. A semiconductor chip as recited in claim 1, wherein:

said portion comprises one of two electrodes within said bulk single crystal semiconductor, said two electrodes comprising a first electrode and a second electrode, said first electrode providing carriers when said device is in operation, said second electrode receiving carriers when said device is in operation;

a carrier conduction region formed within said bulk single crystal semiconductor, said carrier conduction region located between said first and said second electrodes;

first and second conductive connectors contacting respectively said first and second electrodes; and

a control electrode providing control over the flow of carriers in said carrier conduction region, said control electrode provided in said first horizontal trench.

17. A semiconductor chip as recited in claim 16, wherein said first electrode comprises a first heavily doped region, said second electrode comprises a second heavily doped region, said carrier conduction region comprises a first channel region, and said control electrode comprises a gate electrode comprising a first gate insulator formed on a surface of said first horizontal trench and a first gate conductor formed on a surface of said first gate insulator, said first gate insulator being said first material.

18. A semiconductor chip as recited in claim 17, further comprising:

a second horizontal trench buffed within said bulk single crystal substrate;

a second gate insulator formed on a surface of said second horizontal trench;

a second gate conductor formed on a surface of said second gate insulator;

a third and a fourth heavily doped region adjacent said second gate insulator; and

third and fourth conductive connectors in contact respectively with said third and fourth heavily doped regions.

19. A semiconductor chip as recited in claim 18, wherein said first horizontal trench and said second horizontal trench are the same.

20. A semiconductor chip as recited in claim 19, wherein said second and forth conductive connectors comprise a vertical conductor interconnecting said second heavily doped region with said fourth heavily doped region.

21. A semiconductor chip as recited in claims 20, further comprising an invertor, said invertor comprising said interconnected transistors.

22. A semiconductor chip as recited in claim 18, wherein said first and third heavily doped regions and said second and fourth heavily doped regions are the same.

23. A semiconductor chip as recited in claim 16, further comprising a second horizontal trench adjacent one of said first and said second electrodes, wherein said conductive connector extends through said second horizontal trench.

24. A semiconductor chip, comprising:

a bulk single crystal substrate;

a first horizontal trench buried within said bulk single crystal substrate, said first horizontal trench comprising a surface of bulk single crystal substrate;

an electronic device having a first portion adjacent said first horizontal trench, said first portion being within said bulk single crystal substrate, said device further comprising a second portion within said first horizontal trench;

a vertical trench intersecting said portion; and

a first electrically conductive material extending through said vertical trench and forming a contact with said portion.

25. A semiconductor chip as recited in claim 24, wherein said first electrically conductive material contacts said surface of said first horizontal trench.

26. A semiconductor chip as recited in claim 25, further comprising a first layer of insulation on said first electrically conductive material.

27. A semiconductor chip as recited in claim 26, wherein said first layer of insulation does not fill said first horizontal trench.

28. A semiconductor chip as recited in claim 24, wherein said contact comprises a Schottky barrier.

29. A semiconductor chip as recited in claims 24, wherein said bulk single crystal semiconductor adjacent said first horizontal trench contains an element diffused from said first electrically conductive material.

30. A semiconductor chip as recited in claim 24, wherein said device is one of a bipolar transistor, an FET, and a diode.

31. A semiconductor chip as recited in claim 24, wherein said portion is a collector of a bipolar transistor.

32. A semiconductor chip as recited in claim 24, further comprising:

a second layer of insulation on a surface of said first horizontal trench; and

a second electrically conductive material on said second layer of insulation.

33. A semiconductor chip as recited in claim 32, wherein said second layer of insulation is a gate dielectric and said second layer of electrically conductive material comprises a gate conductor.

34. A semiconductor chip as recited in claim 24, further comprising a second insulator formed on a surface of said first horizontal trench whereby said second insulator provides dielectric isolation for said portion.

35. A semiconductor chip as recited in claim 34, wherein said second insulator does not completely fill said first horizontal trench.

36. A semiconductor chip as recited in claim 24, wherein:

said portion comprises one of two electrodes within said bulk single crystal semiconductor, said two electrodes comprising a first electrode and a second electrode, said first electrode providing carriers when said device is in operation, said second electrode receiving carriers when said device is in operation;

a carrier conduction region formed within said bulk single crystal semiconductor, said carrier conduction region located between said first and said second electrodes;

first and second conductive connectors contacting respectively said first and second electrodes; and

a control electrode providing control over the flow of carriers in said carrier conduction region, said control electrode provided in said first horizontal trench.

37. A semiconductor chip as recited in claim 36, wherein said first electrode comprises a first heavily doped region, said second electrode comprises a second heavily doped region, said carrier conduction region comprises a first channel region, and said control electrode comprises a gate electrode comprising a first gate insulator formed on a surface of said first horizontal trench and a first gate conductor formed on a surface of said first gate insulator.

38. A semiconductor chip as recited in claims 37, further comprising:

a second horizontal trench buried within said bulk single crystal substrate;

a second gate insulator formed on a surface of said second horizontal trench;

a second gate conductor formed on a surface of said second gate insulator;

a third and a fourth heavily doped region adjacent said second gate insulator; and

third and fourth conductive connectors in contact respectively with said third and fourth heavily doped regions.

39. A semiconductor chip as recited in claim 38, wherein said first horizontal trench and said second horizontal trench are the same.

40. A semiconductor chip as recited in claim 39, further comprising a vertical conductor interconnecting a first diffusion of said first FET with a second diffusion of said second FET.

41. A semiconductor chip as recited in claim 40, further comprising an invertor, said invertor comprising said interconnected transistors.

42. A semiconductor chip as recited in claim 38, wherein said first and third heavily doped regions and said second and fourth heavily doped regions are the same.

43. A semiconductor chip as recited in claim 36, further comprising a second horizontal trench adjacent one of said first and said second electrodes, wherein said conductive connector extends through said second horizontal trench.

44. A semiconductor chip, comprising:

a bulk crystal semiconductor having a conventional planar surface;

a first three-terminal device disposed in a first plane parallel to said surface comprising first and second electrodes within said bulk single crystal semiconductor, and a third control electrode that controls electrical connection between said first and second electrodes when said is operational;

a second three-terminal device disposal in a second plane parallel to said surface comprising forth and fifth electrodes within said bulk single crystal semiconductor, and a sixth control electrode that controls electrical connection between said forth and fifth electrodes when said device is operational, a terminal of said second device being vertically displaced with respect to a respective terminal of said first device, said first device being connected to said second device;

a vertical trench adjacent said first electrode; and

a first conductive connector contacting said first electrode, said first conductive connector extending through said vertical trench.

45. A semiconductor chip as recited in claim 44, said first and second three terminal devices being FETs, said first, second, fourth, and fifth electrodes being source/drain regions and said third and sixth control electrodes being gates.

46. A semiconductor chip as recited in claim 45, said vertically displaced terminal of said second device being said sixth control electrode, said sixth control electrode being a gate.

47. A semiconductor chip as recited in claim 45, said vertically displaced terminal of said second device comprising a source/drain region.

48. A semiconductor chip as recited in claim 44, wherein said first device shares an electrode with said second device.