Method and apparatus for connecting and disconnecting a power field effect transistor

• US 5,583,384 A
• Filed: 06/07/1995
• Issued: 12/10/1996
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Henry, Paul M.
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): PALADINI, ALBERT WILLIAM
• Application Number:
  US08/473,806
• Time in Patent Office: 552 Days
• Field of Search: 307/112, 307/113, 327/404, 257/328, 257/213, 257/288, 257/351, 429/99, 429/56, 363/49, 320/51, 320/53, 320/54, 320/59, 320/60, 361/15
• US Class Current: 307/113
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A power switch includes two power FETs connected back-to-back in series at a common source node and a common gate node and a resistor connected between the common source node and the common gate node. The switch further includes a current source and a single-control switch connected to the current source and to the gate node for switching the current source to the gates of the two power FETs.

Claims

1. A power switch comprising:

two power FETs coupled back-to-back in series at a common source node and a common gate node;

a resistor coupled between the common source node and the common gate node; and

a FET coupled to the two power FETs and coupled to the resistor.

2. A switch according to claim 1 wherein the two power FETs include:

a first N-channel MOSFET having a source terminal coupled to a first end of the resistor, a drain terminal and a gate terminal coupled to the second end of the resistor; and

a second N-channel MOSFET having a source terminal coupled to the source terminal of the first N-channel MOSFET and coupled to the first end of the resistor, a drain terminal and a gate terminal coupled to the gate terminal of the first N-channel MOSFET and to the second end of the resistor.

3. A switch according to claim 2 further comprising:

a high voltage P-channel MOSFET having a source terminal and having a drain terminal coupled to the gate terminals of the first and second N-channel MOSFETs and coupled to the second end of the resistor.

4. A switch according to claim 3 further comprising:

a current source;

a switch coupling the current source to the source terminal of the high voltage P-channel MOSFET.

5. A switch according to claim 1 further comprising:

two diodes respectively coupled across the source/drain pathways of the two power FETs, the diodes being conductive from source to drain of respective power FETs.

6. A switch according to claim 5 wherein the diodes are body-drain diodes.

7. A switch according to claim 1 further comprising:

a battery coupled in series with the two power FETs, the power FETs being used to connect and disconnect the battery.

8. A switch according to claim 7 further comprising:

a first terminal at a first end of the series-connected battery and power FETs; and

a second terminal at a second end of the series-connected battery and power FETs, the first and second terminals for connecting a positive terminal and a negative terminal of a battery charger.

9. A switch according to claim 1 further comprising:

a current source; and

a control switch coupled to the current source and to the gate node for switching the current source to the gates of the two power FETs.

10. A switch according to claim 1 wherein the resistor is a relatively large resistor having a resistance in a range from approximately 100KΩ

to 20MΩ

.

32. A switch according to claim 3 further comprising:

a current source;

a switch coupling the current source to the source terminal of the high voltage P-channel MOSFET.

11. A battery pack comprising:

two power FETs coupled back-to-back in series at a common source node and a common gate node;

a resistor coupled between the common source node and the common gate node; and

a controller having a control terminal coupled to the common gate node to control the two power FETs.

12. A battery pack according to claim 11 wherein the controller further comprises:

a transistor coupled to the two power FETs at the common gate node;

an electrical source; and

a switch coupling the electrical source to the transistor.

13. A battery pack according to claim 11 wherein the controller further comprises:

a FET coupled to the two power FETs at the common gate node;

a current source; and

a switch coupling the current source to the FET.

14. A battery pack according to claim 11 wherein the two power FETs include:

a first N-channel MOSFET having a source terminal coupled to a first end of the resistor, a drain terminal and a gate terminal coupled to the second end of the resistor; and

a second N-channel MOSFET having a source terminal coupled to the source terminal of the first N-channel MOSFET and coupled to the first end of the resistor, a drain terminal and a gate terminal coupled to the gate terminal of the first N-channel MOSFET and to the second end of the resistor.

15. A battery pack according to claim 14 wherein the controller further comprises:

a high voltage FET coupled to the two power FETs at the common gate node, the high voltage FET including;

a high voltage P-channel MOSFET having a source terminal and having a drain terminal coupled to the gate terminals of the first and second N-channel MOSFETs and coupled to the second end of the resistor;

a current source; and

a switch coupling the current source to the high voltage FET.

16. A battery pack according to claim 11 further comprising:

two diodes respectively coupled across the source/drain pathways of the two power FETs, the diodes being conductive from source to drain of respective power FETs.

17. A battery pack according to claim 16 wherein the diodes are body-drain diodes.

18. A battery pack according to claim 11 further comprising:

a battery coupled in series with the two power FETs, the power FETs being used to connect and disconnect the battery.

19. A battery pack according to claim 18 further comprising:

a first terminal at a first end of the coupled battery and power FETs; and

a second terminal at a second end of the series-connected battery and power FETs, the first and second terminals for connecting a positive terminal and a negative terminal of a battery charger.

20. A battery pack according to claim 11 wherein the controller further comprises:

a current source; and

a control switch coupled to the current source and to the gate node for switching the current source to the gates of the two power FETs.

21. A battery pack according to claim 11 wherein the resistor is a relatively large resistor having a resistance in a range from approximately 0.1MΩ

to 20MΩ

.

22. A method of connecting and disconnecting a battery from a circuit comprising the steps of:

coupling two power FETs back-to-back in series at a common source node and a common gate node;

coupling a resistor between the common source node and the common gate node; and

coupling a battery in series with the two power FETs, the power FETs being used to connect and disconnect the battery.

23. A method according to claim 22, further comprising the step of:

sourcing a current through the resistor so that a first power FET and a second power FET of the two power FETs are conductive.

24. A method according to claim 23, further comprising the step of:

removing the current through the resistor so that the first power FET and the second power FET of the two power FETs are nonconductive.

25. A method according to claim 22, further comprising the step of:

connecting a battery charger in parallel with the series-connected battery and power FETs.

26. A method according to claim 25, further comprising the step of:

sourcing a current through the resistor so that a first power FET and a second power FET of the two power FETs are conductive.

27. A method according to claim 26, further comprising the step of:

removing the current through the resistor so that the first power FET and the second power FET of the two power FETs are nonconductive.

28. A power switch comprising:

two power FETs coupled back-to-back in series including a first power FET having a source terminal and a gate terminal and a second power FET having a source terminal directly coupled to the source terminal of the first power FET at a common source node and a gate terminal directly coupled to the gate terminal of the first power FET at a common gate node; and

a resistor coupled between the common source node and the common gate node.

29. A switch according to claim 28 further comprising:

a FET coupled to the two power FETs and coupled to the resistor.

30. A switch according to claim 28 wherein the two power FETs include:

a first N-channel MOSFET having a source terminal coupled to a first end of the resistor, a drain terminal and a gate terminal coupled to the second end of the resistor; and

a second N-channel MOSFET having a source terminal coupled to the source terminal of the first N-channel MOSFET and coupled to the first end of the resistor, a drain terminal and a gate terminal coupled to the gate terminal of the first N-channel MOSFET and to the second end of the resistor.

31. A switch according to claim 30 further comprising:

a high voltage P-channel MOSFET having a source terminal and having a drain terminal coupled to the gate terminals of the first and second N-channel MOSFETs and coupled to the second end of the resistor.

33. A switch according to claim 28 further comprising:

two diodes respectively coupled across the source/drain pathways of the two power FETs, the diodes being conductive from source to drain of respective power FETs.

34. A switch according to claim 33 wherein the diodes are body-drain diodes.

35. A switch according to claim 28 further comprising:

a battery coupled in series with the two power FETs, the power FETs being used to connect and disconnect the battery.

36. A switch according to claim 35 further comprising:

a first terminal at a first end of the series-connected battery and power FETs; and

a second terminal at a second end of the series-connected battery and power FETs, the first and second terminals for connecting a positive terminal and a negative terminal of a battery charger.

37. A switch according to claim 28 further comprising:

a current source; and

a control switch coupled to the current source and to the gate node for switching the current source to the gates of the two power FETs.

38. A switch according to claim 28 wherein the resistor is a relatively large resistor having a resistance in a range from approximately 100KΩ

to 20MΩ

.