Differentially coupled AND/NAND and XOR/XNOR circuitry

• US 5,583,456 A
• Filed: 08/25/1995
• Issued: 12/10/1996
• Est. Priority Date: 08/25/1994
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kimura, Katsuji
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US08/519,172
• Time in Patent Office: 473 Days
• Field of Search: 326/112, 326/115, 326/121
• US Class Current: 326/115
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors

Abstract

Disclosed is a semiconductor integrated circuit which have a pair of transistors Q11, Q12 with a first polarity being differentially inputted with first logical values A(+) and A(-), a first constant current source I11 for driving the pair of transistors with the first polarity, two pairs of transistors Q13, Q14 and Q15, Q16 with a second polarity, each of the two pairs of transistors being differentially inputted with second logical values B(+) and B(-) and being connected to a drain of each of the pair of transistors with the first polarity, a second and third constant current sources I12, I13 for driving the two pairs of transistors, respectively, and load resistors R11, R12 which are connected to the two pairs of transistors, respectively. The two pairs of transistors Q13-Q16 have one transistor Q13 being connected to one of the load resistors and the other three transistors Q14-Q16 being connected to the other of the load resistors, and an AND output is obtained from a node of one transistor Q13 and the load resistor R11 and an NAND output is obtained from a node of the other three transistors Q14-Q16 and the load resistor R12.

Claims

1. A semiconductor integrated circuit, comprising:

a first pair of transistors of first polarity differentially inputted with first logical values, sources of said first pair of transistors being interconnected;

a first constant current source for driving said first pair of transistors of said first polarity;

second and third pairs of transistors of second polarity, each of said second and third pairs of transistors being differentially inputted with second logical values, the sources of each of said second and third pairs of transistors being interconnected and respectively connected to drains of said first pair of transistors;

second and third constant current sources for driving said second and third pairs of transistors, respectively; and

load resistors connected to said second and third pairs of transistors, respectively.

4. The semiconductor integrated circuit of claim 1 further comprising:

an inverter/non-inverter circuit having a fourth pair of transistors, said fourth pair of transistors being differentially inputted with one of said first and second logical values, whereby operating points and modes of said first, second, third and fourth pairs of transistors are identical without utilizing a level shift circuit in said semiconductor integrated circuit.

2. A semiconductor integrated circuit, comprising:

a first pair of transistors of first polarity differentially inputted with first logical values, sources of said first pair of transistors being interconnected;

a first constant current source for driving said first pair of transistors;

second and third pairs of transistors of second polarity, each of said second and third pairs of transistors being differentially inputted with second logical values, sources of each of said second and third pairs of transistors being interconnected and respectively connected to drains of said first pair of transistors;

second and third constant current sources for driving said second and third pairs of transistors, respectively; and

load resistors which are connected to said second and third pairs of transistors, respectively;

wherein one transistor from said second pair of transistors is connected to one of said load resistors, and the remaining transistors from said second and third pairs of transistors are connected to another of said load resistors, and a NAND output is obtained from a node between said one transistor and said one of said load resistors, and an AND output is obtained from a node between said remaining transistors and said another of said load resistors.

5. The semiconductor integrated circuit of claim 2 further comprising:

an inverter/non-inverter circuit having a fourth pair of transistors, said fourth pair of transistors being differentially inputted with one of said first and second logical values, whereby operating points and modes of said first, second, third and fourth pairs of transistors are identical without utilizing a level shift circuit in said semiconductor integrated circuit.

3. A semiconductor integrated circuit, comprising:

a first pair of transistors of first polarity differentially inputted with first logical values, sources of said first pair of transistors being interconnected;

a first constant current source for driving said first pair of transistors;

second and third pairs of transistors of second polarity, said second pair of transistors comprising first and second transistors differentially inputted with second logical values and said third pair of transistors comprising third and fourth transistors differentially inputted with said second logical values, sources of said first and second transistors being interconnected and connected to a drain of one transistor of said first pair of transistors, sources of said third and fourth transistors being interconnected and connected to a drain of the other transistor of said first pair of transistors;

second and third constant current sources for driving said second and third pairs of transistors, respectively; and

load resistors which are connected to said second and third pairs of transistors, respectively;

wherein drains of said first and third transistors are connected to one of said load resistors, said first and third transistors being differentially inputted, and drains of said second and fourth transistors are connected to another of said load resistors, said second and fourth transistors being differentially inputted, and wherein an EXOR output is obtained from a node between said first and third transistors and said one of said load resistors and an EXNOR output is obtained from a node between said second and fourth transistors and said another of said load resistors.

6. The semiconductor integrated circuit of claim 3 further comprising:

an inverter/non-inverter circuit having a fourth pair of transistors, said fourth pair of transistors being differentially inputted with one of said first and second logical values, whereby operating points and modes of said first, second, third and fourth pairs of transistors are identical without utilizing a level shift circuit in said semiconductor integrated circuit.