Signal processing system and method

• US 5,583,506 A
• Filed: 07/22/1988
• Issued: 12/10/1996
• Est. Priority Date: 07/22/1988
• Status: Expired due to Fees

• Current Assignee: Northrop Grumman Corporation
• Original Assignee: Northrop Grumman Corporation
• Inventors: Gardner, Michael J., Fry, David B., Sinor, Susan S., Fitzgerald, Alfred B. III, Zagardo, Vincent S., Horner, William D., Mowery, David L., Kiselewich, Gary M., Vanous, Michael D., Ferguson, Lynn D.
• Primary Examiner(s): CANGIALOSI, SALVATORE A
• Application Number:
  US07/223,091
• Time in Patent Office: 3,063 Days
• Field of Search: 364/200, 364/900, 364/131-133, 342/25
• US Class Current: 342/25.00R
• CPC Class Codes: G01S 7/285 Receivers
• CPC Class Codes: G01S 7/292 Extracting wanted echo-signals
• CPC Class Codes: G01S 7/295 Means for transforming co-ordinates or for evaluating data, e.g. using computers

Abstract

An avionic digital signal processing system for a plurality of different types of input sensors such as radar, electro-optical, and electronic warfare that comprises a PI bus operating at 12.5 MHz and a data network subbus operating at 20 MHz. A plurality of array processor groups each having a plurality of 1750 CPU'"'"'s are controlled over the PI-bus and receive their sensor inputs over the subbus data network. A plurality of general purpose 1750A computers are connected to the PI-bus for communicating control and narrow band information. A distributed operating system resides in the 1750A central processing units and includes provision for re-routing the signal paths in the event of failure of modules.

Claims

1. A digital signal processing system for controlling avionic displays and devices in accordance with processed signals from a plurality of sensors, comprising

a plurality of array processor groups, each group including bulk memory means for storing sensor received data, signal processing means for processing the stored data, and controller means for handling the storage and processing of the data;

subbus data network means interconnecting the bulk memory means, the signal processing means, and control means of each respective array processor group, and interconnecting the plurality of groups in parallel relationship for storing sensed data in a bulk memory means of a selected array group and for processing and transferring the stored and processed data to selected array groups in accordance with the control means of a selected one of the array groups;

a plurality of individual general purpose digital computers;

an input/output module means for receiving and generating instructions to operate the avionic displays and devices; and

parallel interface bus means interconnecting each of the general purpose computers, the input/output module means, and the control means of each array processor group in parallel relationship to one another for generating the signals to operate the display and avionic devices in accordance with the processed signals.

2. The digital signal processing system of claim 1, wherein the bulk memory means of each group, comprises a central processing unit, a plurality of memory elements, an input/output switch having an input and output port for each of the plurality of memory elements, a control element connecting the plurality of memory elements in parallel to the ports for transferring data from any one of the plurality of memory elements to any one of the plurality of output ports.

3. The digital signal processing system of claim 1 wherein the signal processing means, comprises a plurality of signal processing elements, input/output switch means having a number of input/output ports connected to the processing elements and to the bulk memory means, and a control element for operating the input/output switch for operatively connecting the bulk memory means to a selected one of the signal processing elements.

4. The digital signal processing means of claim 1 wherein the subbus data network means, comprises a bidirectional multibit data bus having an asynchronous input/output switch with a plurality of ports operative at different clock rates for transferring data to a selected array group.

5. The digital signal processing means of claim 1 wherein the subbus data network means comprises a bidirectional multibit data bus having a synchronous input/output switch with a plurality of ports operative at the identical clock rate for transferring data from one array group to another.

6. The digital signal processing means of claim 1 wherein the parallel interface bus means comprises a master/slave protocol permitting the bus master to read data from one slave or to write data to any number of slaves in a single message sequence.

7. The digital signal processing system of claim 1, further comprising a plurality of sensors operatively coupled in parallel relationship to the data network, one of said plurality being a radar antenna and another of said plurality being an electronic warfare sensor.

8. A digital signal processing system for controlling avionic displays and devices in accordance with processed signals from a pluraltiy of sensors, comprising

a subbus data network means having a plurality of gate array elements for creating and destroying data paths, one of said elements being an asynchronous element having a plurality of ports operative at different clock rates, said subbus data nework being clocked at a first maximum clock rate;

a plurality of array processor groups, each group including bulk memory means for storing sensor received data, signal processing means for processing the stored data, and controller means for handling the storage and processing of the data, said controller means of each group being operatively coupled in parallel relationship to the parallel interface bus, said bulk memory means of each group being operatively coupled to the data newtork means;

a plurality of sensor means operatively coupled to the data network means for transferring data information to the bulk memory means;

distributed operating system program means residing in the controller means of each array group for controlling the data processed in the signal prpocessing means; and

means operatively coupled to the parallel interface bus responsive to the processed signals for operating avionic devices in accordance with the characteristics of the sensed processed signals.

9. The digital signal processor of claim 8 wherein the signal processing mean of at least one array group is operative to process partially the sensed signals, and said system further comprises a plurality of individual general purpose digital computers operatively coupled to the parallel interface bus for completing the processing of the partially processed signals.

10. The digital signal processing system of claim 8, wherein the bulk memory means and controller means of each group each comprise a pair of central processing units, one central processing unit of each respective pair being operatively connected to run application programs for processing the sensed signals in the bulk memory means and signal processing means respectively, and the other central processing unit of each pair being commonly coupled for handling control messages, each of said other units of each pair having a memory operatively shared with one another.

11. The digital signal processing system of claim 8 wherein the plurality of gate array elements for creating and destroying data paths, further comprises a synchronous element having a plurality of ports each operative at the same first maximum clock rate.

12. The digital signal processing system of claim 8 wherein the distributed operating system includes a system executive program, and comprises means responsive to fault indications and status requests of modules coupled to the Parallel interface bus for reconfiguring the system to compensate for the failed module and inform the system executive program of the reconfigured status.

13. The digital signal processing system of claim 8 wherein the distributed operating system, comprises means for detecting the complete failure and the disconnection of a module from the parallel interface bus.

14. The digital signal processing system of claim 8, wherein the bulk memory means of each group, comprises at least one central processing unit, a plurality of memory elements, an input/output switch having an input and output port for each of the plurality of memory elements, a control element connecting the plurality of memory elements in parallel to the ports for transferring data from any one of the plurality of memory elements to any one of the plurality of output ports in accordance with instructions from the central processing unit.

15. The digital signal processing system of claim 8 wherein the signal processing means, comprises a plurality of signal processing elements, input/output switch means having a number of input/output ports connected to the processing elements and to the bulk memory means, and a controller for operating the input/output switch for operatively connecting the bulk memory means to selected ones of the signal processing elements.

16. The digital signal processing means of claim 15, wherein the bulk memory means comprises a plurality of bulk memory elements, input/output switch means with a plurality of ports operative at different clock rates for transferring data between selected ones of the bulk memory elements to selected ones of the signal processing elements.

17. The digital signal processing means of claim 16 wherein the input/output switch means of the signal processing means and the bulk memory means are operable to permit the transfer of data between the plurality of signal processing elements, between the plurality of bulk memory elements and the plurality of signal processing elements, and between the signal processing elements and the controller.

18. The digital signal processing means of claim 17 wherein the parallel interface bus means comprises a master/slave protocol permitting the bus master to read data from one array group or to write data to any number of array groups in a single message sequence.

19. The digital signal processing system of claim 18 wherein the parallel interface bus includes means for operating at a speed of approximately 12.5 MHz.

20. The digital signal processing system of claim 19 wherein the data network includes means for clocking at a rate of 20 MHz.

21. The digital signal processing system of claim 17, wherein the input/output switch means is operable to permit transfers of data from one selected signal processing element to all other signal processing elements, transfers of data between adjacent signal processing elements, and transfers between any signal processor elements in accordance with a stored lookup table.

22. A method of processing signals received from a plurality of different types of avionic sensors in a digital processing system having an input/output module, a generl purpose computer, an array processor group for processing the sensed signals, a plurality of different types of sensor input, a subbus data network connecting the processor group and sensor input in parallel relationship, and a parallel interface bus connecting the array processor group and input/output module and general purpose computer in parallel relationship independent of the sensors and the data network, said method comprising

transferring data from the sensors input over the subbus data network to the array processor group for processing the sensed input,

transferring data representative of post detection information from the array processor group to the general purpose computer over the parallel interface bus,

transferring data representative of avionic system mode commands between the general purpose computer and the input/output module over the parallel interface bus,

processing signal processing mode commands in response the post detection information in the general purpose computer,

transferring the processed signal processing mode commands from the general purpose digital computer to the array processor group over the parallel interface bus for processing the sensed input in accordance with the mode commands, and

transferring control and narrow band data into and out of the input/output module.

23. The method of claim 22 wherein the data is transferred over the subbus data network at a rate substantially faster than the data is transferred over the parallel interface bus.

24. The method of processing signals received from a plurality of different types of avionic sensors in a digital processing system having an input/output module, a plurality of general purpose computers, a plurality of array processor groups for processing the sensed signals, a plurality of different types of sensor input, a subbus data network connecting the array processor groups and sensor input in parallel relationship, and a parallel interface bus connecting the plurality of array processor groups and input/output module and the plurality of general purpose computers in a parallel relationship independent of the sensors and the data network, and an operating system that resides in each central processing unit of the plurality of general purpose computers and the plurality of array processor groups, said method comprising the steps of

scheduling and synchronization of application processes,

reading and writing data between two modules and between a module and an outside entity via the parallel interface bus,

responding to and monitoring fault indications and status requests of each module in the system, and

handling of interrupts.

25. The method of claim 24 wherein the step of scheduling and synchronizing, comprises the substeps of

defining the processes within a processor module based upon a set of attributes,

allocating the module for the execution of the processes,

scheduling the processes for changing a process form one state to another, said states being one of the undefined, dormant, waiting, ready, and active states,

executing the processes, and

synchronizing the processes with semaphores and events.

26. The method of claim 24 wherein the step of reading and writing data comprises the substep of

communicating between two parallel interface bus labels, and determining the completion of a transfer with the use of semaphores.

27. The method of claim 24 wherein the step of responding to asnd monitoring fault indications and status requests of each module in the system, comprises the substeps of

monitoring the health of the parallel interface bus, interconnecting buses, and loss of a processor module, and

determining a suitable reconfiguration to compensate for an unhealthy component.

28. The method of claim 24 wherein the step of responding to and monitoring fault indications and status requests, comprises the substeps of

detecting a periodic signal transmitted from each module, and

detecting a periodic signal transmitted from each module, and

initiating a reconfiguration upoon the failure to detect said signal for a predetermined time period.

29. The method of claim 24 wherein the step of handling the interrupts, comprises the substeps of selectively

calling a procedure from the step of process scheduling for signalling the proper semaphore or event, and

forwarding the message associated with the interrupt for one of the process scheduling and synchronization of application processes, reading and writing data, and responding to and monitoring fault indications.

30. The method of claim 24 wherein the distributed operating system and application programs run on respective one of a pair of central processing units of each array processor group, and the step of process scheduling, comprises the substeps of

utilizing an area of memory for sharing between each one of the pair of central processing units to pass parameters,

executing both central processing units of the pair concurrently, performing a central processing unit output call on the unit running the application software, and

continuing execution of code on the unit running the application software following the output call while the unit running the distributed output system is performing the output.