Column electrode drive circuit of liquid crystal display device capable of simultaneously applying display voltages to column electrodes as well as sequentially applying scanning voltages to column electrodes

• US 5,583,535 A
• Filed: 08/19/1994
• Issued: 12/10/1996
• Est. Priority Date: 08/24/1993
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Takarada, Takeshi, Kawanishi, Junji
• Primary Examiner(s): SARAS, STEVEN J
• Application Number:
  US08/292,196
• Time in Patent Office: 844 Days
• Field of Search: 345/104, 345/87, 345/92, 345/98, 345/99, 345/100, 345/173, 345/175, 345/182, 345/205, 345/213, 178/18
• US Class Current: 345/99
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0441 using active external devices, e.g. active pens, for receiving changes in electrical potential transmitted by the digitiser, e.g. tablet driving signals
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3681 suitable for passive matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

There is provided a column electrode drive circuit applicable to a display-integrated type tablet. A hold circuit has a plurality D-flip-flops. To clock terminals of the flip-flops is input an output signal of an AND circuit which receives inputs of a hold signal and a clock signal. To data terminals of the flip-flops are input sampled display signals. With the above-mentioned arrangement, when the hold signal is at "H" level, the sampled display signals are sequentially output as display signals without modification based on the clock signal. When the hold signal is a pulse signal, the sampled display signals are simultaneously output and held as the display signals. By thus making a simultaneous output function and a sequential output function compatible, the column electrode drive circuit can be utilized as a column electrode drive circuit for the display-integrated type tablet device.

Claims

1. A column electrode drive circuit of a liquid crystal display device, said column electrode drive circuit having a sampling circuit for sequentially sampling a display signal corresponding to display pixels in synchronization with a clock signal supplied thereto, a hold circuit for holding the display signal sampled, and an output circuit for outputting to each column electrode a voltage signal corresponding to the display signal held, said pixels of a column of a pixel matrix being connected to a column electrode via respective switching elements, wherein

the hold circuit includes a plurality of flip-flops which are arranged in parallel with each other for holding the display signals input from the sampling circuit and in synchronization with a periodic hold signal supplied to a clock terminal of each of the flip-flops simultaneously outputting the display signals to the column electrodes, and for sequentially outputting the display signals sequentially input from the sampling circuit to the column electrodes in synchronization with the clock signal supplied to the clock terminal when a continuous hold signal is supplied to said hold circuit, and

a clock signal supply circuit for supplying the same frequency clock signal supplied to the sampling circuit and the hold signal to the clock terminal of each of the flip-flops.

2. A column electrode drive circuit of a liquid crystal display device as claimed in claim 1, wherein

the clock signal supply circuit is a signal selector circuit which takes in the hold signal and the clock signal to select and output the hold signal to the clock terminal of each of the flip-flops in an image display period, and to select and output the clock signal to the clock terminal in a vertical retrace interval.

3. A column electrode drive circuit of a liquid crystal display device as claimed in claim 1, further comprising

a frequency divider circuit responsive to a shift clock signal having a given frequency for dividing the given frequency of the shift clock signal by a specified number to output a frequency-divided clock signal, and

a switching circuit which selects the frequency-divided clock signal from the frequency divider circuit as the clock signal in a vertical retrace interval of the device and which selects the shift clock signal as the clock signal in an image display period of the device responsive to an external switching signal to selectively output the frequency-divided clock signal or the shift clock signal,

said sampling circuit sequentially sampling the display signal on a cycle of the frequency-divided clock signal which is longer than a cycle of the given frequency of the shift clock signal based on the frequency-divided clock signal in the vertical retrace interval, and said hold circuit being responsive to the frequency-divided clock signal applied to the clock terminal of each of the flip-flops and sequentially outputting the display signals sequentially sampled on the cycle of the frequency-divided clock signal by the sampling circuit to the output circuit based on the frequency-divided clock signal in the vertical retrace interval.

4. A column electrode drive circuit of a liquid crystal display device as claimed in claim 2, further comprising

a frequency divider circuit responsive to a shift clock signal having a given frequency for dividing the given frequency of the shift clock signal by a specified number to output a frequency-divided clock signal, and

a switching circuit which selects the frequency-divided clock signal from the frequency divider circuit as the clock signal in the vertical retrace interval and which selects the shift clock signal as the clock signal in the image display period responsive to an external switching signal to selectively output the frequency-divided clock signal or the shift clock signal,

said sampling circuit sequentially sampling the display signal on a cycle of the frequency-divided clock signal which is longer than a cycle of the given frequency of the shift clock signal based on the frequency-divided clock signal in the vertical retrace interval, and said hold circuit being responsive to the frequency-divided clock signal applied to the clock terminal of each of the flip-flops and sequentially outputting the display signals sequentially sampled on the cycle of the frequency-divided clock signal by the sampling circuit to the output circuit based on the frequency-divided clock signal in the vertical retrace interval.

5. A column electrode drive circuit of a liquid crystal display device as in claim 1 further comprising:

a clock signal producing circuit responsive to an external switching signal for producing a clock signal such that the frequency of the clock signal supplied to the sampling circuit and to the hold circuit is lower when the display signals are sequentially output from the hold circuit than when the display signals are simultaneously output to the column electrodes.

6. A column electrode drive circuit of a liquid crystal display device, said column electrode drive circuit having sampling circuits for sequentially sampling display signals corresponding to each pixel of a pixel matrix to sequentially produce sampled voltages in synchronization with a clock signal, and hold circuits for holding voltages corresponding to the sampled voltages produced by the sampling circuits, whereby the voltages held are applied to a column electrode connected to a switching element which are provided for each pixel of a pixel matrix, wherein

the hold circuits comprise a plurality of transfer gates which are arranged in parallel with each other and which simultaneously pass sampled voltages from the sampling circuit in synchronization with a transfer signal input thereto, and which sequentially pass the sampled voltages produced by the sampling circuits to the column electrodes when a continuous control signal is input to the hold circuits, and

a plurality of hold capacitors which are arranged in parallel with each other and which hold electric charges corresponding to the sampled voltages which have passed through the corresponding transfer gates,

a signal selector circuit for selecting the transfer signal or the continuous control signal for input to the transfer gates, and

a clock signal producing circuit responsive to an external signal for producing said clock signal such that the frequency of the clock signal is lower when the sampled voltages are sequentially passed than when the sampled voltages are simultaneously passed.

7. A column electrode drive circuit of a liquid crystal display device as claimed in claim 6, wherein

the signal selector circuit is a gate circuit which outputs the transfer signal to the transfer gates in an image display period, and outputs the continuous control signal to the transfer gates in a vertical retrace interval.

8. A column electrode drive circuit in a liquid crystal display device as claimed in claim 7, wherein said clock signal producing circuit includes:

a frequency divider circuit responsive to a shift clock signal having a given frequency for dividing the given frequency of the shift clock signal by a specified number to output a frequency-divided clock signal, and

a switching circuit which selects the frequency-divided clock signal from the frequency divider circuit as the clock signal in the vertical retrace interval, and which selects the shift clock signal as the clock signal in the image display period responsive to said external switching signal to selectively output the frequency-divided clock signal or the shift clock signal,

said sampling circuits sequentially sampling the display signal and sequentially outputting the sampled voltages to the transfer gates on a cycle of the frequency-divided clock signal which is longer than a cycle of the given frequency of the shift clock signal based on the frequency-divided clock signal in the vertical retrace interval.