System and method for transmitting a plurality of digital services including imaging services

• US 5,583,562 A
• Filed: 12/03/1993
• Issued: 12/10/1996
• Est. Priority Date: 12/03/1993
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Scientific-Atlanta Incorporated (Cisco Systems, Inc.)
• Inventors: Van Staden, Christian V., Birch, Christopher H., Nicholas, Paul D., Lawrence, Steven S., Brooks, Walter R.
• Primary Examiner(s): Peng, John K.
• Assistant Examiner(s): GRANT, CHRISTOPHER C
• Application Number:
  US08/161,160
• Time in Patent Office: 1,103 Days
• Field of Search: 348/12, 348/10, 348/13, 348/725, 348/726, 348/500, 348/507, 348/508, 348/513, 348/720, 348/901, 348/555, 348/554, 348/556, 348/558, 348/384, 348/423, 348/471, 348/472, 358/86, 455/5.1, 455/6.1, 455/3.2
• US Class Current: 725/151
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/007 Unequal error protection for format H04L1/0078; for codes per se H03M13/35
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 1/0083 Formatting with frames or packets; Protocol or part of protocol for error control
• CPC Class Codes: H04L 1/22 using redundant apparatus to increase reliability
• CPC Class Codes: H04L 2001/0098 Unequal error protection
• CPC Class Codes: H04N 21/236 Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream multiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/2383 Channel coding or modulation of digital bit-stream, e.g. QPSK modulation arrangements for detecting or preventing errors in the information received by adapting the channel coding H04L1/0009; analogue front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/2385 Channel allocation H04N21/266 takes precedence; Bandwidth allocation H04N21/24 takes precedence ; allocation of channels according to the instantaneous demands of the users in time-division multiplex systems H04J3/1682; admission control, resource allocation in open networks H04L12/5692; arrangements for maintenance or administration in data switching networks involving bandwidth and capacity management H04L41/0896; negotiating bandwidth in wireless networks H04W28/16
• CPC Class Codes: H04N 21/242 Synchronization processes, e.g. processing of PCR [Program Clock References] arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4302 Content synchronisation processes, e.g. decoder synchronisation
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 7/1675 Providing digital key or authorisation information for generation or regeneration of the scrambling sequence pseudo-random number generators in general G06F7/58
• CPC Class Codes: H04N 7/20 Adaptations for transmission via a GHz frequency band, e.g. via satellite

Abstract

A multiplex frame format for transmitting digital data in a data transmission system comprises a PACKETS portion comprising a highly error-protected region and a region having only Reed Solomon encoding as an error protection measure, the PACKETS portion including low speed data. The frame format also comprises portions for transmitting medium (AUDIO) and high speed (VIDEO) data streams following the PACKETS portion. Prior to transmission, the composed frame comprising the PACKETS, AUDIO and VIDEO portions is interleaved and the BLOCK SYNC and FRAME SYNC are added. A multiplex structure control packet word of the PACKETS portion immediately follows FRAME SYNC. Thus, the FRAME SYNC word defines where interleaving begins. A demultiplexer in concert with a microcontroller of a decoder decodes the multiplex structure control word and related PACKETS and outputs digital data streams to related output peripheral processors. The BLOCK SYNC word preferably comprises one eight bit byte and contains network signaling or other data at predetermined bit positions within the word. Moreover, the frame format is flexible and may vary in horizontal and vertical dimensions as digital service streams are varied due to service requirements or priorities. The multiplexers for forming the frame according to the present invention may be arranged in redundant (hot standby) or in multi-service arrangements synchronized by a synchronizing waveform, digitally generated to comprise a continuous 3.375 MHz portion and a single cycle frame marking signal of greater magnitude but significantly lower frequency.

Claims

1. In a receiver for receiving digital data streams transmitted in a frame format comprising rows and columns, the first row of the frame comprising a horizontal synchronization word followed by a vertical synchronization word, apparatus for decoding the horizontal synchronizing word comprising

means for storing the identity of predetermined respective locations of block synchronization data and other data of a horizontal synchronization word,

means for recovering the horizontal synchronization word,

means for extracting the other data at the predetermined locations and

means for forming a data stream from the extracted other data.

2. The apparatus of claim 1 wherein the horizontal synchronization word is binary comprising alternating values.

3. The apparatus of claim 2 wherein the horizontal synchronization word comprises one eight bit byte and the block synchronization data and other data each comprise four bits.

4. The apparatus of claim 1 wherein the means for recovering the horizontal synchronization word comprises frequency comparison means.

5. The apparatus of claim 1 wherein the means for recovering the horizontal synchronization word comprises means for comparing the block synchronization data with a predetermined binary pattern.

6. The apparatus of claim 1 wherein the predetermined bit positions of the other data are in predetermined sequence and the other data comprises network signaling data.

7. Apparatus for decoding a horizontal synchronizing word according to claim 1, said data stream forming means for extracting at least one bit of other data per frame and combining a plurality of said at least one bit received over at least two frames into said data stream.

8. Apparatus for decoding a horizontal synchronizing word according to claim 1, further including means, responsive to said data stream of said data stream forming means from the extracted other data, for interpreting said data stream as at least one of network signalling, telecommunications identification, transmitter identification, logical connector order, maintenance, and alarm information.

9. Apparatus for decoding the horizontal synchronizing word according to claim 7, further including means, responsive to said data stream of said data stream forming means, for interpreting said data stream as at least one of network signalling, telecommunications identification, transmitter identification, logical connector order, maintenance, and alarm information.

10. In a receiver for receiving digital data streams transmitted in a frame format comprising rows and columns, the first row of the frame comprising a horizontal synchronization word followed by a vertical synchronization word, a method for decoding the horizontal synchronizing word comprising the steps of

storing the identity of predetermined locations of block synchronization and other data of a horizontal synchronization word,

recovering the horizontal synchronization word,

extracting the other data at the predetermined locations and

forming a data stream from the extracted other data.

11. The method of claim 10 wherein the block synchronization data is binary comprising alternating one and zero values.

12. The method of claim 11 wherein the horizontal synchronization word comprises one eight bit byte and block synchronization and the other data each comprise four bits.

13. The method of claim 10 wherein the step for recovering the horizontal synchronization word comprises comparison with a predetermined frequency represented by the horizontal synchronization word.

14. The method of claim 10 wherein the step for recovering the horizontal synchronization word comprises comparing the horizontal synchronization word with a predetermined pattern.

15. The method of claim 10 wherein the predetermined bit positions of the other data are in predetermined sequence and the other data comprises network signaling data.

16. The method for decoding the horizontal synchronizing word according to claim 10, said step of forming a data stream from the extracted other data including the step of extracting at least one bit of other data per frame and combining a plurality of said at least one bit received over at least two frames into said data stream.

17. The method for decoding the horizontal synchronizing word according to claim 10, further including the step of interpreting said data stream as at least one of network signalling, telecommunications identification, transmitter identification, logical connector order, maintenance, and alarm information.

18. In a receiver for receiving digital data streams transmitted in a frame format comprising rows and columns, the first row of the frame comprising a horizontal synchronization word immediately followed by a vertical synchronization word, the vertical synchronization word immediately followed by a multiplex structure control word, wherein the frame comprises PACKETS data of different types determined by the number of bytes in a particular type of packet and the multiplex structure control word comprises data representing the number of packets of a particular type, and end of data markers for the digital data streams, apparatus for decoding the multiplex structure control word comprising

synchronization recovery means for recovering horizontal and vertical synchronization for the frame and

demultiplexer means, responsive to the synchronization recovery means, for demultiplexing the digital data streams in accordance with the multiplex structure control word said demultiplexer means including counters for determining the end of each received stream from said multiplex structure control word.

19. The apparatus for decoding the multiplex structure control word according to claim 18, said demultiplexer means outputting at least one of an error flag, data, clock, and enable signals.

20. The apparatus for decoding the multiplex structure control word according to claim 18, said demultiplexer means controlling in accordance with said multiplex structure control word at least one of a video processor, an audio processor, a text processor, and a low speed data processor.

21. The apparatus for decoding the multiplex structure control word according to claim 18, further including an expansion socket receiving at least one of data, an error flag, a clock signal, and a frame synchronization signal.

22. In a receiver for receiving digital data streams transmitted in a frame format comprising rows and columns, the first row of the frame comprising a horizontal synchronization word immediately followed by a vertical synchronization word, the vertical synchronization word immediately followed by a multiplex structure control word, apparatus for recovering the low speed data comprising

synchronization recovery means for recovering horizontal and vertical synchronization for the frame,

demultiplexer means, responsive to the synchronization recovery means, for demultiplexing the low speed data from the low speed data packets in accordance with the multiplex structure control word,

a low speed data processor for processing low speed data packets, the low speed data processor comprising a stripping means for stripping header data from the received packet and a data reformatter for reformatting the data into an originally input format, and

buffer memory wherein the data reformatter outputs data from the buffer memory in data bursts at a faster rate than the data is stored in the buffer memory.

23. The apparatus of claim 22 wherein the low speed data processor decodes rata trim data of the header.

24. The apparatus of claim 22 wherein the low speed data processor decodes baud rate data of the header.

25. The apparatus for recovering the low speed data according to claim 22, said frame format further including high speed data packets containing high speed data, said demultiplexing means further including means for demultiplexing the high speed data from the high speed data packets in accordance with the multiplex structure control word.

26. In receiver apparatus for receiving a signal including high speed data streams, the high speed data stream including at least a digital television data stream, a high speed data processor comprising

decoder means for decoding a packet data portion of the received signal including a high definition television signal flag,

first output means, responsive to said decoder means, for outputting a received television signal, and

second output means, responsive to said decoder means, for outputting a high definition television signal indicator signal when the output television signal is a high definition television signal.

27. The high speed data processor according to claim 26, wherein said decoder means outputs at least one of data, an error flag, a clock signal, and a frame synchronization signal and said first output means receives said at least one of data, an error flag, a clock signal, and a frame synchronization signal.

28. The high speed data processor according to claim 27, further receiving an audio data stream and including an audio processor for responding to said audio data stream and said at least one of data, an error flag, a clock signal, and a frame synchronization signal and for outputing an audio signal.

29. The high speed data processor according to claim 27, further receiving a text data stream and including a text processor for responding to said text data stream and said at least one of data, an error flag, a clock signal, and a frame synchronization signal and for outputing a text signal.

30. The high speed data processor according to claim 27, further receiving a low speed data stream and including a low speed data processor for responding to said low speed data stream and said at least one of data, an error flag, a clock signal, and a frame synchronization signal and outputs a low speed data signal.

31. The high speed data processor according to claim 26, further including an expansion socket receiving said at least one of data, an error flag, a clock signal, and a frame synchronization signal.