Long write test
First Claim
1. A method of performing long write testing of a static memory device, comprising the steps of:
- selecting a portion of a static memory device to subject to a long write test during a test mode, wherein the selected portion of the static memory device has a plurality of wordlines, a plurality of bitlines, and a plurality of address signals, including a plurality of row address signals and a plurality of column address signals;
writing to the plurality of bitlines within the selected portion of the static memory device simultaneously for a predetermined period of time, thereby performing a long write test;
recovering the plurality of bitlines within the selected portion of the static memory device; and
read disturbing the selected portion of the static memory device.
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Accused Products
Abstract
According to the present invention, a block of a static memory device, or some portion thereof, is selected to be subjected to a long write test. Choosing a portion of the static memory device, such as a block, offers the advantage of limiting current switching transients as well as recovery time following the long write test. All bitlines of the selected block are written to simultaneously for a period of time; all the wordlines within the selected block are disabled during this time so that no memory cell is selected. The bitlines of the selected block are recovered in two phases so that current switching transients are limited to a reasonable value and writing to the bitlines may be staggered. Finally, the selected block is read disturbed by cycling row fast through the selected block.
29 Citations
48 Claims
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1. A method of performing long write testing of a static memory device, comprising the steps of:
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selecting a portion of a static memory device to subject to a long write test during a test mode, wherein the selected portion of the static memory device has a plurality of wordlines, a plurality of bitlines, and a plurality of address signals, including a plurality of row address signals and a plurality of column address signals; writing to the plurality of bitlines within the selected portion of the static memory device simultaneously for a predetermined period of time, thereby performing a long write test; recovering the plurality of bitlines within the selected portion of the static memory device; and read disturbing the selected portion of the static memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of performing long write testing of a static memory device, comprising the steps of:
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selecting a portion of a static memory device to subject to a long write test during a test mode, wherein the selected portion of the static memory device has a plurality of wordlines, a plurality of bitlines, and a plurality of address signals, including a plurality of row address signals and a plurality of column address signals; switching an address signal of the plurality of address signals from a first logic state to a second logic state, such that only a portion of the plurality of bitlines is written to simultaneously; writing to the plurality of bitlines within the selected portion of the static memory device simultaneously for a predetermined period of time, thereby performing a long write test; recovering the plurality of bitlines within the selected portion of the static memory device; and read disturbing the selected portion of the static memory device, wherein when the address signal is equal to the first logic state, a true derivative signal of the address signal is equal to the first logic state and a complement derivative signal of the address signal is equal to the second logic state, thereby defining a staggering condition;
when the address signal is equal to the second logic state, the true derivative signal and the complement derivative signal are both equal to the first logic state, thereby defining an enabling condition. - View Dependent Claims (22, 23)
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24. A structure to perform long write testing of a static memory device, comprising:
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a selected portion of a static memory device having a plurality of wordlines, a plurality of bitlines, and a plurality of address signals, including a plurality of row address signals and a plurality of column address signals; and an address buffer circuit which controls the plurality of address signals to perform the long write testing of the static memory device, wherein the address buffer circuit comprises; an address bond pad having an address signal of the plurality of address signals; a first inverting element having the address signal as an input terminal and producing an output signal that is inverted with respect to the address signal, wherein the output signal of the first inverting element is an address complement signal produced by the address buffer circuit; a passgate, having the address complement signal as an input signal, controlled by a first address override signal and a second address override signal to selectively pass the address complement signal as an output signal, wherein when the first address override signal is a first logic level and the second address override signal is a second logic level, the selected portion of the static memory device is placed in a test mode; a pull-up element, having a first terminal electrically connected to a first supply voltage and a second terminal electrically connected to the output signal of the passgate, controlled by a first control signal; a pull-down element, having a first terminal electrically connected to the output signal of the passgate and a second terminal electrically connected to a second supply voltage, controlled by a second control signal; a second inverting element, having an input terminal electrically connected to a node comprised of the output signal of the passgate, the second terminal of the pull-up element, and the first terminal of the pull-down element, which produces an address true signal of the address buffer circuit; wherein the address complement signal is controlled by the address signal and the address true signal is controlled by the first control signal and the second control signal, such that when the first control signal is the second logic level the passgate is turned off and the address true signal is equal to the second logic level, and when the second control signal is the first logic level the passgate is turned off and the address true signal is equal to the first logic level. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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Specification