Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage
First Claim
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1. A memory device, comprising:
- a storage cell having a storage node for holding a logic state indicative of a first data value, wherein the logic state lies within a range of voltages defined by upper and lower supply voltages;
a bit line associated with the storage cell;
a pass transistor coupled to the bit line and the storage node of the storage cell;
a biasing circuit, coupled to the pass transistor, for selectively forward-biasing and reverse-biasing the pass transistor with a first bias voltage which is approximately equal to the upper supply voltage and a second bias voltage which is lower than the lower supply voltage, respectively, regardless of whether the storage node is maintained at a logical 1 or a logical 0.
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Abstract
A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.
30 Citations
23 Claims
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1. A memory device, comprising:
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a storage cell having a storage node for holding a logic state indicative of a first data value, wherein the logic state lies within a range of voltages defined by upper and lower supply voltages; a bit line associated with the storage cell; a pass transistor coupled to the bit line and the storage node of the storage cell; a biasing circuit, coupled to the pass transistor, for selectively forward-biasing and reverse-biasing the pass transistor with a first bias voltage which is approximately equal to the upper supply voltage and a second bias voltage which is lower than the lower supply voltage, respectively, regardless of whether the storage node is maintained at a logical 1 or a logical 0. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of providing a memory device, comprising the steps of:
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providing a storage cell having a storage node for holding a logic state indicative of a data value, wherein the logic state lies within a range of voltages defined by upper and lower supply voltages; providing a bit line associated with the storage cell; providing a pass transistor coupled to the bit line and the storage node of the storage cell; and providing a biasing circuit, coupled to the pass transistor, for selectively forward-biasing and reverse-biasing the pass transistor with a first bias voltage which is approximately equal to the upper supply voltage and a second bias voltage which is lower than the lower supply voltage, respectively, regardless of whether the storage node is maintained at a logical 1 or a logical 0. - View Dependent Claims (17)
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18. A method of operating a memory cell including a storage node for holding a logic state indicative of a first data value, a bit line associated with the memory cell, and a pass transistor coupled between the storage node and the bit line, wherein the logic state lies within a range of voltages defined by upper and lower supply voltages, the method comprising the step of:
selectively forward-biasing and reverse-biasing the pass transistor with a first bias voltage which is approximately equal to the upper supply voltage and a second bias voltage which is lower than the lower supply voltage, respectively, regardless of whether the storage node is maintained at a logical 1 or a logical 0. - View Dependent Claims (19, 20, 21, 22, 23)
Specification