Single chip controller-memory device and a memory architecture and methods suitable for implementing the same

• US 5,583,822 A
• Filed: 11/01/1995
• Issued: 12/10/1996
• Est. Priority Date: 05/09/1994
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Rao, G. R. Mohan
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/551,526
• Time in Patent Office: 405 Days
• Field of Search: 365/230.03, 365/230.06, 345/188, 345/193, 345/200
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 29/80 with improved layout
• CPC Class Codes: G11C 29/81 using a hierarchical redundancy scheme
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method is provided for operating a memory including a plurality of blocks of memory cells and a plurality of address decoders, each address decoder allowing access to selected cells in a corresponding one of the blocks in response to selected row and column address bits presented substantially simultaneously on an associated address bus. A first set of row and column address bits are presented on the address bus to access selected cells in a first selected one of the blocks via an associated data bus coupled to each of the blocks. A second set of row and column address bits are then presented on the address bus to access selected cells in a second selected one of the blocks via the data bus.

Claims

1. A method of generating display images comprising the steps of:

writing digital display data into selected cells in selected blocks of a multi-block memory, each block associated with a dedicated address decoder for allowing access to selected cells therein in response to selected row and column address bits presented substantially simultaneously on an associated address bus;

presenting a first set of row and column address bits on the address bus to read digital data written into selected cells of a first selected one of the blocks via an associated data bus coupled to each the blocks;

presenting a second set of row and column address bits on the address bus to read digital data written selected cells in a second selected one of the blocks via the data bus; and

converting the digital data read from the first and second blocks into analog data for driving a display device.

2. The method of claim 1 wherein the digital data read from the first and second blocks is in a YUV format and the method further comprises the step of converting the YUV data read from the first and second blocks into RGB data.

3. The method of claim 1 and further comprising the step of selectively zooming the data read from the first and second blocks.

4. The method of claim 1 wherein said steps of writing and presenting are performed by a display controller integral with the memory.

5. A method of operating an integrated controller--memory device, the device including a controller, a plurality of blocks of memory cells, and a plurality of address decoders, each address decoder allowing access to selected cells in a corresponding one of the blocks in response to selected row and column address bits presented substantially simultaneously on an associated address bus by the controller, the method comprising the steps of:

presenting a first set of row and column address bits on the address bus with the controller;

accessing selected cells in a first selected one of the blocks in response to the first set of address bits via an associated data bus coupled to each the blocks;

presenting a second set of row and column address bits on the address bus with the controller; and

accessing selected cells in a second selected one of the blocks via the data bus in response to the second set of address bits.

6. The method of claim 5 wherein the steps of presenting are performed sequentially to implement an interleaved access of the first and second blocks.

7. The method of claim 5 wherein the steps of presenting are performed substantially concurrently and the steps of accessing are performed substantially simultaneously, wherein each of the first and second blocks is accessed via to respective first and second portions of the data bus.

8. The method of claim 5 wherein the integrated device further includes a digital to analog converter and the method includes the step of converting digital data read from the selected blocks during read accesses into analog data.

9. A method of operating a memory including a plurality of blocks of memory cells and a plurality of address decoders, each address decoder allowing access to selected cells in a corresponding one of the blocks in response to selected row and column address bits presented substantially simultaneously on an associated address bus, the method comprising the steps of:

presenting a first set of row and column address bits on the address bus to access selected cells in a first selected one of the blocks via an associated data bus coupled to each the blocks; and

presenting a second set of row and column address bits on the address bus to access selected cells in a second selected one of the blocks via the data bus.

10. The method of claim 9 wherein said steps of presenting address bits are performed to effectuate interleaved accesses from the first and second selected blocks.

11. The method of claim 10 wherein the data bus is n-bits wide and each of the interleaved accesses an n-bit location in the corresponding selected block.

12. The method of claim 9 wherein said steps of presenting effectuate substantially simultaneous accesses to the first and second selected blocks.

13. The method of claim 12 wherein said first and second sets of addresses are presented substantially simultaneously on the address bus.

14. The method of claim 12 wherein the data bus has a predetermined width and the first and second accesses are each to a number of cells representing a portion of the width of the bus.