DC level control for an electronic telephone line card

• US 5,583,934 A
• Filed: 03/03/1995
• Issued: 12/10/1996
• Est. Priority Date: 03/03/1995
• Status: Expired due to Term

• Current Assignee: Microsemi Semiconductor (U.S.) Inc. (Microchip Technology Incorporated)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Zhou, Yan
• Primary Examiner(s): Zele, Krista M.
• Assistant Examiner(s): TEBCHERANI, GLOR
• Application Number:
  US08/398,295
• Time in Patent Office: 648 Days
• Field of Search: 379/283, 379/282, 379/280, 379/385, 379/377, 379/399, 379/361, 375/317, 327/77
• US Class Current: 379/399.02
• CPC Class Codes: H04M 19/005 Feeding arrangements without the use of line transformers
• CPC Class Codes: H04M 3/005 Interface circuits for subscriber lines current supply H04M19/00 and subgroups; supervisory, monitoring or testing arrangements H04M3/22 and subgroups; in key telephone systems H04M9/006

Abstract

DC level control for an electronic telephone line card which filters the DC component from the input audio signal, determines the gain setting of the transmit path, develops a DC adjust voltage opposite to that of the DC shift component and subtracts the DC adjust voltage to the input voltage to cancel the DC shift component. A quantized, discontinuous feedback path is implemented to respond only to DC shifts so the AC operation remains substantially unaffected. Such discontinuous feedback eliminates stability and impedance matching problems introduced with continuous feedback solutions. A DC control circuit according to the present invention includes a low pass filter for detecting DC shifts, a quantizer for asserting an incremental signal, a threshold detector for activating adjustment functions, and an accumulator for developing the DC adjust voltage by incremental steps. A long term low pass filter and reset circuit resets the accumulator to cancel residual DC adjust voltages which might otherwise reduce the dynamic range of the telephone line transmit path.

Claims

1. A DC control circuit for cancelling DC voltage shifts occurring on the input signal of a telephone line card, the telephone line card including an AC input amplifier and a transmit path for detecting and converting the input signal to digital values, said DC control circuit comprising:

a filter for receiving the transmit path digital values and for filtering and detecting DC voltage shifts of the digital values to provide a DC shift signal indicative thereof;

an adjust circuit coupled to said low pass filter and receiving said DC shift signal for providing a quantized signal;

an accumulator coupled to said adjust circuit and receiving said quantized signal for developing a DC adjust voltage; and

an adder coupled to said accumulator and for coupling to the AC input amplifier for subtracting said DC adjust voltage from the input signal.

2. The DC control circuit of claim 1, wherein said filter is a low pass filter having a cutoff frequency of approximately 40 hertz.

3. The DC control circuit of claim 1, wherein the level of said quantized signal is based on the maximum voltage and gain of the transmit path of the telephone line card.

4. The DC control circuit of claim 1, wherein said quantized level is zero when said DC shift signal is below a predetermined threshold level.

5. The DC control circuit of claim 4, wherein said predetermined threshold level is equal to half the magnitude of the maximum voltage of the transmit path of the telephone line card.

6. The DC control circuit of claim 1, wherein the telephone line card includes a gain amplifier in the transmit path and wherein said adjust circuit comprises:

a quantizer receiving said DC shift signal and asserting said quantized signal at predetermined quantization levels;

a duplicate amplifier receiving said DC shift signal and having the same gain as the transmit amplifier of the telephone line card, said duplicate amplifier providing an amplified DC shift signal;

a threshold circuit comparing said amplified DC shift signal to a predetermined threshold level and providing an adjust signal indicative thereof; and

a switch circuit having an input receiving said quantized signal, a control terminal receiving said adjust signal and an output for providing said quantized signal while said amplified DC shift signal is equal to or greater than said predetermined threshold level.

7. The DC control circuit of claim 6, wherein said quantized signal is asserted at the same polarity as said DC shift signal and at a predetermined magnitude if the absolute value of said DC shift signal is greater than or equal to said predetermined magnitude, but otherwise said quantized signal is zero.

8. The DC control circuit of claim 1, wherein said accumulator comprises:

an adder for adding said quantized signal to a delayed summation signal for providing a summation signal;

a delay device receiving said summation signal from said adder for providing said delayed summation signal after a predetermined delay; and

a digital to analog converter for converting said summation signal to said DC adjust signal.

9. The DC control circuit of claim 1, wherein said predetermined delay is 1 millisecond or less.

10. The DC control circuit of claim 1, further including a reset circuit coupled to said accumulator and receiving the transmit path digital values for resetting said accumulator, said reset circuit comprising:

a long term filter for detecting a residual DC value on said digital values;

a first threshold circuit for detecting whether said DC adjust voltage is zero and providing a zero signal indicative thereof;

said adjust circuit providing an adjust signal indicative of whether said DC shift signal is above said predetermined threshold level;

an adder coupled to said accumulator and said long term filter for combining said residual DC value with said DC adjust signal and providing a residual detect signal;

a second threshold circuit for determining whether said residual detect signal is above a predetermined threshold level; and

a switch circuit coupled to said first and second threshold circuits and said adjust circuit for resetting said accumulator output to zero.

11. The DC control circuit of claim 10, wherein said long term filter is a long term DC level predictor and a narrow band low pass filter.

12. The DC control circuit of claim 10, wherein said switch circuit comprises:

a logic gate receiving said zero signal, said adjust signal and said residual detect signal for providing a reset signal; and

a switch coupled to provide digital zero values to said accumulator when said reset signal is asserted, wherein said DC adjust voltage goes to zero.

13. A telephone line card for receiving an audio signal from a telephone, comprising:

an input detection amplifier for separating the metallic component of the audio signal;

an analog to digital converter for receiving and converting said analog metallic signal to a digital signal;

a decimator for converting said digital signal to a decimated digital signal;

a transmit path amplifier receiving and amplifying said decimated digital signal at a programmed gain;

a low pass filter receiving said decimated digital signal for filtering and detecting DC voltage shifts for providing DC shift signals indicative thereof;

an adjust circuit receiving said DC shift signal for providing a quantized signal;

an accumulator receiving said quantized signal for developing a DC adjust voltage; and

an adder coupled to said input detection amplifier, receiving said DC adjust voltage and for receiving the audio signal for subtracting said DC adjust voltage from the audio signal.

14. The telephone line card of claim 13, wherein said quantized signal is based on the maximum voltage and gain of said transmit path amplifier.

15. The telephone line card of claim 13, wherein said adjust circuit asserts said quantized signal at the same polarity as said DC shift signal and at a predetermined magnitude if the absolute value of said DC shift signal is greater than or equal to said predetermined magnitude, but otherwise asserts said quantized signal at zero.

16. The telephone line card of claim 13, wherein said adjust circuit comprises:

a quantizer receiving said DC shift signal and asserting said quantized signal at predetermined quantization levels;

a duplicate amplifier receiving said DC shift signal and having the same programmed gain as said transmit path amplifier for providing an amplified DC shift signal;

a threshold circuit receiving and comparing said amplified DC shift signal to a predetermined threshold level and providing an adjust signal indicative thereof; and

a switch circuit receiving said quantized signal and said adjust signal for providing said quantized signal to said accumulator while said adjust signal indicates said amplified DC shift signal is greater than or equal to said predetermined threshold level, but otherwise providing zero.

17. The telephone line card of claim 16, wherein said predetermined threshold level is equal to half the maximum output magnitude of said transmit path amplifier.

18. The telephone line card of claim 13, wherein said accumulator comprises:

an adder for adding said quantized signal to a delayed summation signal for providing a DC adjust signal; and

a delay device for receiving said DC adjust signal and providing said delayed summation signal.

19. The telephone line card of claim 18, further comprising:

a digital to analog converter for converting said DC adjust signal to said DC adjust voltage.

20. The telephone line card of claim 13, further including a reset circuit receiving said decimated digital signal and providing a reset signal to reset said accumulator, said reset circuit comprising:

a long term DC level predictor filter receiving said decimated digital signal for providing a residual DC value;

a first threshold circuit for detecting whether said DC adjust voltage is zero and providing a zero signal indicative thereof;

said adjust circuit providing an adjust signal indicative of whether said DC shift signal is above said predetermined threshold level;

an adder coupled to said accumulator and said long term filter for adding said residual DC value to said DC adjust signal and providing a residual detect signal;

a second threshold circuit for determining whether said residual detect signal is above a second predetermined threshold level; and

a switch circuit coupled to said first and second threshold circuits and said adjust circuit for resetting said accumulator output to zero.

21. The telephone line card of claim 20, wherein said switch circuit comprises:

a logic gate receiving said zero signal, said adjust signal and said residual detect signal for providing a reset signal; and

a switch coupled to provide a zero value to said accumulator when said reset signal is asserted, wherein said DC adjust voltage goes to zero.

22. A telephone system, comprising:

a telephone including a DTMF generator, wherein said telephone asserts audio signals and dial tones from said DTMF generator onto a two-wire interface;

a telephone line card coupled to said two-wire interface for receiving said audio signals, said telephone line card comprising;

an input detection amplifier for separating the metallic component of the audio signal, and for providing an analog metallic signal,

an analog to digital converter for receiving and converting said analog metallic signal to a digital signal;

a decimator for decimating said digital signal for providing a decimated digital signal;

a transmit path amplifier receiving and amplifying said decimated digital signal at a programmed gain;

a filter receiving said decimated digital signal for filtering and detecting DC voltage shifts for providing DC shift signals indicative thereof;

an adjust circuit receiving said DC shift signal for providing a quantized signal;

an accumulator receiving said quantized signal for developing a DC adjust voltage; and

an adder coupled to said input detection amplifier, receiving said DC adjust voltage and for receiving the audio signal for subtracting said DC adjust voltage from the audio signal; and

a compression unit coupled to said transmit path amplifier for converting amplified decimated digital signals to PCM codes; and

a PCM highway coupled to said telephone line card for transmitting and receiving PCM codes.

23. The telephone system of claim 22, wherein said adjust circuit comprises:

a quantizer receiving said DC shift signal and asserting said quantized signal at a predetermined quantization level having the same polarity of said DC shift signal while the absolute value of said DC shift signal is greater than or equal to said predetermined quantization level, but otherwise asserting said quantized signal at zero;

a duplicate amplifier receiving said DC shift signal and having the same programmed gain as said transmit path amplifier for providing an amplified DC shift signal;

a threshold circuit receiving and comparing said amplified DC shift signal to a predetermined threshold level and providing an adjust signal indicative thereof; and

a switch circuit receiving said quantized signal and said adjust signal for providing said quantized signal to said accumulator while said adjust signal indicates said amplified DC shift signal is greater than or equal to said predetermined threshold level, but otherwise providing zero.

24. The telephone system of claim 22, wherein said telephone line card includes a reset circuit receiving said decimated digital signal and providing a reset signal to reset said accumulator, said reset circuit comprising:

a long term filter receiving said decimated digital signal for providing a residual DC value;

a first threshold circuit for detecting whether said DC adjust voltage is zero and providing a zero signal indicative thereof;

said adjust circuit providing an adjust signal indicative of whether said DC shift signal is above said predetermined threshold level;

an adder coupled to said accumulator and said long term filter for combining said residual DC value with said DC adjust signal and providing a residual detect signal;

a second threshold circuit for determining whether said residual detect signal is above a second predetermined threshold level; and

a switch circuit coupled to said first and second threshold circuits and said adjust circuit for resetting said accumulator output to zero.