Kernel processor system

• US 5,584,032 A
• Filed: 03/22/1993
• Issued: 12/10/1996
• Est. Priority Date: 10/17/1984
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US08/034,627
• Time in Patent Office: 1,359 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/400, 395/425, 395/375, 395/800, 395/100, 395/116, 395/118, 395/126, 395/127, 395/128, 395/129, 395/132, 395/401, 395/405
• US Class Current: 711/100
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06T 5/20 using local operators
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A kernel processor system having a buffer memory, a kernel memory, and a kernel processor provides improved kernel processing capability. The disclosed arrangement comprises an input circuit generating input information; a buffer memory storing buffered information; a write address circuit generating write addresses; a buffer memory write access circuit writing buffered information into the buffer memory in response to the input information and in response to the write addresses; a read address circuit generating read addresses; a buffer memory read access circuit generating buffered output information in response to the buffered information and in response to the read addresses; a kernel memory storing a kernel of information in response to the buffered output information; a kernel processor generating filtered output information in response to the kernel of information; and a display monitor displaying a filtered image in response to the filtered output information.

Claims

1. A kernel processor system comprising:

a first line buffer storing a first line of display information;

a second line buffer storing a second line of display information;

a third line buffer storing a third line of display information;

an input circuit coupled to the first line buffer, coupled to the second line buffer, and coupled to the third line buffer and writing the first line of display information into the first line buffer;

a first output circuit coupled to the second line buffer and outputting the second line of display information from the second line buffer;

a second output circuit coupled to the third line buffer and outputting the third line of display information from the third line buffer;

a kernel memory coupled to the first output circuit and coupled to the second output circuit and storing a kernel of display information in response to the second line of display information output by the first output circuit and in response to the third line of display information output by the second output circuit; and

a kernel processor coupled to the kernel memory and generating a line of spatially filtered display information in response to the kernel of display information stored by the kernel memory.

4. A kernel processor system as set forth in claim 1, wherein the kernel memory comprises a kernel of registers coupled to the first output circuit and coupled to the second output circuit and storing the kernel of display information with the kernel of registers in response to the second line of display information output by the first output circuit and in response to the third line of display information output by the second output circuit.

5. A kernel processor system as set forth in claim 1, wherein the kernel processor comprises:

a plurality of multiplier circuits coupled to receive the kernel of display information stored by the kernel memory, the plurality of multiplier circuits generating product information in response to the received kernel of display information; and

a plurality of adder circuits coupled to receive the product information generated by the plurality of multiplier circuits, the plurality of adder circuits generating the line of spatially filtered display information by summing the received product information.

6. A kernel processor system as set forth in claim 1, wherein the kernel processor comprises:

a weight circuit generating filter weight information;

a plurality of multiplier circuits coupled to receive the kernel of display information stored by the kernel memory and coupled to receive filter weight information generated by the weight circuit, the plurality of multiplier circuits generating product information in response to the received kernel of display information and in response to the received filter weight information; and

a plurality of adder circuits coupled to receive the product information generated by the plurality of multiplier circuits, the plurality of adder circuits generating the line of spatially filtered display information by summing the received product information.

7. A kernel processor system as set forth in claim 1, further comprising a display monitor coupled to receive the line of spatially filtered display information generated by the kernel processor, the display monitor displaying a filtered image in response to the line of spatially filtered display information.

2. A kernel processor system comprising:

a first line buffer storing a first line of display information;

a second line buffer storing a second line of display information;

a third line buffer storing a third line of display information;

an input circuit coupled to the first line buffer and writing the first line of display information into the first line buffer;

a control circuit coupled to the first line buffer, coupled to the second line buffer, and coupled to the third line buffer and distributing the first line of display information from the first line buffer to the second line buffer and the second line of display information from the second line buffer to the third line buffer;

a first output circuit coupled to the second line buffer and outputting the second line of display information stored by the second line buffer;

a second output circuit coupled to the third line buffer and outputting the third line of display information stored by the third line buffer;

a kernel memory coupled to the first output circuit and coupled to the second output circuit and storing a kernel of display information in response to the second line of display information output by the first output circuit and in response to the third line of display information output by the second output circuit; and

a kernel processor coupled to the kernel memory and generating a line of spatially filtered display information in response to the kernel of display information stored by the kernel memory.

3. A kernel processor system comprising:

a first line buffer storing a first line of display information;

a second line buffer storing a second line of display information;

a third line buffer storing a third line of display information;

an input circuit coupled to the first line buffer and writing the first line of display information into the first line buffer;

a first output circuit coupled to the second line buffer and outputting the second line of display information from the second line buffer;

a second output circuit coupled to the third line buffer and outputting the third line of display information from the third line buffer;

a multiplexing circuit coupled to the first line buffer, coupled to the second line buffer, coupled to the third line buffer, coupled to the first output circuit and coupled to the second output circuit and distributing the first line of display information written into the first line buffer by the input circuit in sequence to the first output circuit and to the second output circuit to output the second line of display information and to output the third line of display information;

a kernel memory coupled to the first output circuit and coupled to the second output circuit and storing a kernel of display information in response to the second line of display information output by the first output circuit and in response to the third line of display information output by the second output circuit; and

a kernel processor coupled to the kernel memory and generating a line of spatially filtered display information in response to the kernel of display information stored by the kernel memory.

8. A kernel processor system comprising:

a first line buffer storing a first line of display information;

a second line buffer storing a second line of display information;

a third line buffer storing a third line of display information;

an input circuit coupled to the first line buffer and writing the first line of display information into the first line buffer;

a double buffer precessional circuit coupled to the first line buffer, coupled to the second line buffer, and coupled to the third line buffer;

the double buffer precessional circuit precessing the first line of display information written into the first line buffer by the input circuit from the first line buffer, to the second line buffer as the second line of display information, and to the third line buffer as the third line of display information,

a first output circuit coupled to the second line buffer and outputting the second line of display information from the second line buffer;

a second output circuit coupled to the third line buffer and outputting the third line of display information from the third line buffer;

a kernel memory coupled to the first output circuit and coupled to the second output circuit and storing a kernel of display information in response to the second line of display information output by the first output circuit and in response to the third line of display information output by the second output circuit; and

a kernel processor coupled to the kernel memory and generating a line of spatially filtered display information in response to the kernel of display information stored by the kernel memory.

9. A kernel processor system comprising:

a plurality of memories including a first memory, a second memory, and a third memory;

an input circuit coupled to the first memory, to the second memory, and to the third memory and writing a first sequence of input words into the first memory, writing a second sequence of input words into the second memory, and writing a third sequence of input words into the third memory;

a first output circuit coupled to the second memory and outputting a first sequence of output words from the second memory;

a second output circuit coupled to the third memory and outputting a second sequence of output words from the third memory;

a kernel memory coupled to the first output circuit and coupled to the second output circuit and storing a kernel of output words in response to the first sequence of output words generated by the first output circuit and in response to the second sequence of output words generated by the second output circuit; and

a kernel processor coupled to the kernel memory and generating a sequence of spatially filtered output words in response to the kernel of output words stored by the kernel memory.

10. A kernel processor system as set forth in claim 9, wherein the kernel memory comprises a kernel of registers coupled to the first output circuit and coupled to the second output circuit and storing the kernel of output words, the kernel of registers storing the kernel of output words in response to the first sequence of output words generated by the first output circuit and in response to the second sequence of output words generated by the second output circuit.

11. A kernel processor system as set forth in claim 9, wherein the kernel processor comprises:

a plurality of multiplier circuits coupled to receive the kernel of output words stored by the kernel memory, the plurality of multiplier circuits generating product words in response to the received kernel of output words; and

a plurality of adder circuits coupled to receive the product words generated by the plurality of multiplier circuits, the plurality of adder circuits summing the received plurality of product words and generating the sequence of spatially filtered output words in response to a sum of the received product words.

12. A kernel processor system as set forth in claim 9, wherein the kernel processor comprises:

a weight circuit generating filter weight information;

a plurality of multiplier circuits coupled to receive the kernel of output words stored by the kernel memory and coupled to receive filter weight information generated by the weight circuit, the plurality of multiplier circuits generating product words in response to the received kernel of output words and in response to the received filter weight information; and

a plurality of adder circuits coupled to receive the product words generated by the plurality of multiplier circuits, the plurality of adder circuits summing the received plurality of product words and generating the sequence of spatially filtered output words in response to a sum of the received product words.

13. A kernel processor system as set forth in claim 9, further comprising a display monitor coupled to receive the sequence of spatially filtered output words generated by the kernel processor, the display monitor displaying a spatially filtered image in response to the received sequence of spatially filtered output words.

14. A kernel processor system comprising:

a plurality of memories including a first memory storing a first sequence of words, a second memory storing a second sequence of words, and a third memory storing a third sequence of words;

an input circuit coupled to the first memory and writing the first sequence of words into the first memory;

a double buffer precessional circuit coupled to the first memory, coupled to the second memory, and coupled to the third memory, the double buffer precessional circuit precessing the first memory, the second memory, and the third memory;

a first output circuit coupled to the second memory and outputting a first sequence of output words from the second memory;

a second output circuit coupled to the third memory and outputting a second sequence of output words from the third memory;

a kernel memory coupled to receive the first sequence of output words output by the first output circuit and coupled to receive the second sequency of output words output by the second output circuit, the kernel memory storing a kernel of output words in response to the received first sequence of output words and in response to the received second sequence of output words; and

a kernel processor coupled to the kernel memory and generating a sequence of spatially filtered output words in response to the kernel of output words stored by the kernel memory.

15. A kernel processor system comprising:

a plurality of memories including a first memory, a second memory, a third memory, and a fourth memory;

an input circuit coupled to the first memory, coupled to the second memory, coupled to the third memory, and coupled to the fourth memory, the input circuit writing a first sequence of input words into the first memory, writing a second sequence of input words into the second memory, writing a third sequence of input words into the third memory, writing a fourth sequence of input words into the fourth memory;

an output circuit coupled to the second memory, coupled to the third memory, and coupled to the fourth memory and outputting a first sequence of output words from the second memory, outputting a second sequence of output words from the third memory, and outputting a third sequence of output words from the fourth memory simultaneously with the writing of the first sequence of input words into the first memory by the input circuit;

a kernel memory coupled to the output circuit and storing a kernel of output words in response to the first sequence of output words, in response to the second sequence of output words, and in response to the third sequence of output words; and

a kernel processor coupled to the kernel memory and generating a sequence of spatially filtered output words in response to the kernel of output words stored by the kernel memory.

16. A kernel processor system as set forth in claim 15, wherein the kernel memory comprises a kernel of registers coupled to the output circuit and storing the kernel of output words with the kernel of registers in response to the first sequence of output words, in response to the second sequence of output words, and in response to the third sequence of output words.

17. A kernel processor system as set forth in claim 15, wherein the kernel processor comprises:

a plurality of multiplier circuits coupled to receive the kernel of output words stored by the kernel memory, the plurality of multiplier circuits generating product words in response to the received kernel of output words; and

a plurality of adder circuits coupled to receive the product words generated by the plurality of multiplier circuits, the plurality of adder circuits summing the received plurality of product words and generating the sequence of spatially filtered output words in response to a sum of the received product words.

18. A kernel processor system as set forth in claim 15, wherein the kernel processor comprises:

a weight circuit generating filter weight information;

a plurality of multiplier circuits coupled to receive the kernel of output words stored by the kernel memory and coupled to receive filter weight information generated by the weight circuit, the plurality of multiplier circuits generating product words in response to the received kernel of output words and in response to the received filter weight information; and

a plurality of adder circuits coupled to receive the product words generated by the plurality of multiplier circuits, the plurality of adder circuits summing the received plurality of product words and generating the sequence of spatially filtered output words in response to a sum of the received product words.

19. A kernel processor system as set forth in claim 15, further comprising a display monitor coupled to receive the sequence of spatially filtered output words generated by the kernel processor, the display monitor displaying a filtered image in response to the received sequence of spatially filtered output words.

20. A kernel processor system comprising:

a plurality of memories including a first memory storing first information, a second memory storing second information, a third memory storing third information, and a fourth memory storing fourth information;

an input circuit coupled to the first memory and writing the first information into the first memory;

a double buffer precessional circuit coupled to the first memory, coupled to the second memory, coupled to the third memory, and coupled to the fourth memory, the double buffer precessional circuit precessing the first memory, the second memory, the third memory, and the fourth memory;

an output circuit coupled to the second memory, coupled to the third memory, and coupled to the fourth memory and outputting a first sequence of output words from the second memory, outputting a second sequence of output words from the third memory, and outputting a third sequence of output words from the fourth memory simultaneously with the writing of the first information into the first memory by the input circuit;

a kernel memory coupled to the output circuit and storing a kernel of output words in response to the first sequence of output words, in response to the second sequence of output words, and in response to the third sequence of output words; and

a kernel processor coupled to the kernel memory and generating a sequence of spatially filtered output words in response to the kernel of output words stored by the kernel memory.

21. A kernel processor system comprising:

an input circuit generating input information;

a buffer memory storing buffered information;

a write address circuit generating write addresses;

a buffer memory write access circuit coupled to receive input information generated by the input circuit and coupled to receive write addresses generated by the write address circuit, the buffer memory write access circuit writing buffered information into the buffer memory in response to the received input information and in response to the received write addresses;

a read address circuit generating read addresses;

a buffer memory read access circuit coupled to receive buffered information stored by the buffer memory and coupled to receive read addresses generated by the read address circuit, the buffer memory read access circuit generating buffered output information in response to the received buffered information and in response to the received read addresses;

a kernel memory coupled to receive the buffered output information generated by the buffer memory read access circuit, the kernel memory storing a kernel of information in response to the received buffered output information;

a kernel processor coupled to receive the kernel of information stored by the kernel memory, the kernel processor generating filtered output information in response to the received kernel of information; and

a display monitor coupled to receive filtered output information generated by the kernel processor, the display monitor displaying a filtered image in response to the received filtered output information.

22. A kernel processor system comprising:

a plurality of memories including a first memory, a second memory, a third memory, and a fourth memory storing sequences of words;

an input circuit coupled to the first memory, coupled to the second memory, coupled to the third memory, and coupled to the fourth memory and writing a first sequence of words into the first memory, writing a second sequence of words into the second memory, writing a third sequence of words into the third memory, and writing a forth sequence of words into the fourth memory;

an output circuit coupled to the second memory, to the third memory and to the fourth memory and outputting a first sequence of output words from the second memory, outputting a second sequence of output words from the third memory, and outputting a third sequence of output words from the fourth memory simultaneously with the writing of the first sequence of words into the first memory by the input circuit; and

a kernel processor coupled to receive the first sequence of output words output by the output circuit, coupled to receive the second sequence of output words output by the output circuit, and coupled to receive the third sequence of output words output by the output circuit, the kernel processor generating a filtered sequence of output words in response to the received first sequence of output words, in response to the received second sequence of output words, and in response to the received third sequence of output words.

25. A kernel processor system as set forth in claim 22, further comprising a control circuit coupled to the input circuit and coupled to the output circuit, the control circuit controlling the input circuit for writing the first sequence of words into the first memory at a first word rate, and the control circuit controlling the output circuit for outputting the first sequence of output words, the second sequence of output words, and the third sequence of output words at a second word rate, wherein the first word rate is higher than the second word rate.

26. A kernel processor system as set forth in claim 22, further comprising a control circuit coupled to the input circuit and coupled to the output circuit, the control circuit controlling the input circuit for writing the first sequence of words into the first memory at a first word rate, and outputting the first sequence of output words, the second sequence of output words, and the third sequence of output words by the output circuit at a second word rate, wherein the first word rate is lower than the second word rate.

27. A kernel processor system as set forth in claim 22, wherein the kernel processor comprises:

a plurality of multiplier circuits coupled to receive the first sequence of output words output by the second memory, coupled to receive the second sequence of output words output by the third memory, and coupled to receive the third sequence of output words output by the fourth memory;

the plurality of multiplier circuits generating product words in response to the received first sequence of output words, in response to the received second sequence of output words, and in response to the received third sequence of output words; and

a plurality of adder circuits coupled to receive the product words generated by the plurality of multiplier circuits, the plurality of adder circuits generating the filtered sequence of output words by summing the received product words.

28. A kernel processor system as set forth in claim 22, wherein the kernel processor comprises:

a weight circuit generating filter weight information;

a plurality of multiplier circuits coupled to receive the first sequence of output words output by the second memory, coupled to receive the second sequence of output words output by the third memory, coupled to receive the third sequence of output words output by the fourth memory, and coupled to receive filter weight information generated by the weight circuit;

the plurality of multiplier circuits generating product words in response to the received first sequence of output words, in response to the received second sequence of output words, in response to the received third sequence of output words, and in response to the received filter weight information; and

a plurality of adder circuits coupled to receive the product words generated by the plurality of multiplier circuits, the plurality of adder circuits generating the filtered sequence of output words by summing the received product words.

29. A kernel processor system as set forth in claim 22, further comprising a display monitor coupled to receive the filtered sequence of output words generated by the kernel processor, the display monitor displaying a filtered image in response to the filtered sequence of output words.

23. A kernel processor system comprising:

a plurality of memories including a first memory storing a first sequence of words, a second memory storing a second sequence of words, a third memory storing a third sequence of words, and a fourth memory storing storing a forth sequence of words;

an input circuit coupled to the first memory and writing the first sequence of words into the first memory;

a control circuit coupled to the first memory, coupled to the second memory, coupled to the third memory, and coupled to the fourth memory, the control circuit distributing the first sequence of words from the first memory, to the second memory, then to the third memory, and then to the fourth memory;

an output circuit coupled to the second memory, coupled to the third memory, and coupled to the fourth memory and outputting a first sequence of output words in response to the second sequence of words stored by the second memory, outputting a second sequence of output words in response to the third sequence of words stored by the third memory, and outputting a third sequence of output words in response to the fourth sequence of words stored by the fourth memory simultaneously with the writing of the first sequence of words into the first memory by the input circuit; and

a kernel processor coupled to receive the first sequence of output words output by the output circuit, coupled to receive the second sequence of output words output by the output circuit, and coupled to receive the third sequence of output words output by the output circuit, the kernel processor generating a filtered sequence of output words in response to the received first sequence of output words, in response to the received second sequence of output words, and in response to the received third sequence of output words.

24. A kernel processor system comprising:

a plurality of memories including a first memory, a second memory, a third memory, and a fourth memory, each storing a sequence of words;

an input circuit coupled to the first memory and writing a sequence of words into the first memory;

a multiplexing circuit coupled to the first memory, coupled to the second memory, coupled to the third memory, coupled to the fourth memory, and coupled to the input circuit, the multiplexing circuit distributing a sequence of words from the input circuit through the plurality of memories;

an output circuit coupled to the second memory, to the third memory and to the fourth memory and outputting a first sequence of output words from the second memory, outputting a second sequence of output words from the third memory, and outputting a third sequence of output words from the fourth memory simultaneously with the writing of the sequence of words into the first memory by the input circuit; and

a kernel processor coupled to receive the first sequence of output words output by the output circuit, coupled to receive the second sequence of output words output by the output circuit, and coupled to receive the third sequence of output words output by the output circuit, the kernel processor generating a filtered sequence of output words in response to the received first sequence of output words, in response to the received second sequence of output words, and in response to the received third sequence of output words.

30. A kernel processor system comprising:

a plurality of memories including a first memory, a second memory, a third memory, and a fourth memory storing sequences of words;

an input circuit coupled to the first memory and writing a first sequence of words into the first memory;

a double buffer precessional circuit coupled to the first memory, coupled to the second memory, coupled to the third memory, and coupled to the fourth memory, the double buffer precessional circuit precessing the first memory, the second memory, the third memory, and the fourth memory;

an output circuit coupled to the second memory, coupled to the third memory, and coupled to the fourth memory, the output circuit outputting a first sequence of output words from the second memory, outputting a second sequence of output words from the third memory, and outputting a third sequence of output words from the fourth memory simultaneously with the writing of the first sequence of words into the first memory by the input circuit; and

a kernel processor coupled to receive the first sequence of output words output by the double buffer precessional circuit, coupled to receive the second sequence of output words output by the double buffer precessional circuit, and coupled to receive the third sequence of output words output by the double buffer precessional circuit, the kernel processor generating a filtered sequence of output words in response to the received first sequence of output words, in response to the received second sequence of output words, and in response to the received third sequence of output words.

31. A process of operating a kernel processor system comprising the acts of:

generating input information;

storing buffered information in a buffer memory;

generating write addresses;

writing the buffered information into the buffer memory in response to the input information and in response to the write addresses;

generating read addresses;

generating buffered output information in response to the buffered information stored in the buffer memory and in response to the read addresses;

storing a kernel of information in response to the buffered output information;

generating filtered output information in response to the kernel of information; and

displaying a filtered image in response to the filtered output information.

32. A process of operating a kernel processor system comprising the acts of:

generating input information;

storing buffered information in a buffer memory;

generating write addresses;

writing the buffered information into the buffer memory in response to the input information and in response to the write addresses;

generating read addresses;

generating buffered output information in response to the buffered information stored in the buffer memory and in response to the read addresses;

storing a kernel of information in response to the buffered output information;

generating filtered output information in response to the kernel of information;

displaying a filtered image in response to the filtered output information; and

making a product in response to the filtered output information.

33. A process of operating a kernel processor system comprising the acts of:

generating input information;

storing double buffered information in a double buffer memory;

double buffering the input information in the double buffer memory and generating double buffered output information in response to the double buffered information stored in the double buffer memory;

storing a kernel of information in response to the double buffered output information; and

generating filtered output information in response to the kernel of output information.

34. A process of operating a kernel processor system comprising the acts of:

generating input information;

storing double buffered information in a double buffer memory;

double buffering the input information in the double buffer memory and generating double buffered output information in response to the double buffered information stored in the double buffer memory;

storing a kernel of information in response to the double buffered output information;

generating filtered output information in response to the kernel of output information; and

making a product in response to the filtered output information.

35. A memory kernel processor comprising:

an input circuit generating input information;

a double buffer memory storing double buffered information;

a write address circuit generating write addresses;

a write access circuit coupled to receive input information generated by the input circuit and coupled to receive write addresses generated by the write address circuit, the write access circuit writing double buffered information into the double buffer memory in response to the received input information and in response to the received write addresses;

a read address circuit generating read addresses;

a read access circuit coupled to receive double buffered information stored by the double buffer memory and coupled to receive read addresses generated by the read address circuit, the read access circuit receiving the double buffered information from the double buffer memory in response to the read addresses and generating a plurality of lines of double buffered output information in response to the received double buffered information;

a kernel memory coupled to receive the plurality of lines of double buffered output information generated by the read access circuit, the kernel memory storing a kernel of information in response to the received plurality of lines of double buffered output information; and

a kernel processor coupled to receive the kernel of information stored by the kernel memory, the kernel processor generating filtered output information in response to the received kernel of information.

36. A kernel processor system as set forth in claim 35, further comprising a display monitor coupled to receive filtered output information generated by the kernel processor, the display monitor displaying a filtered image in response to the received filtered output information.

37. A kernel processor system comprising:

an input circuit generating input information;

a double buffer memory storing double buffered information;

a write address circuit generating write addresses;

a write access circuit coupled to receive input information generated by the input circuit and coupled to receive write addresses generated by the write address circuit, the write access circuit writing double buffered information into the double buffer memory in response to the received input information and in response to the received write addresses;

a read address circuit generating read addresses;

a read access circuit coupled to receive double buffered information stored by the double buffer memory and coupled to receive read addresses generated by the read address circuit, the read access circuit receiving the double buffered information from the double buffer memory in response to the read addresses and generating double buffered output information in response to the received double buffered information and in response to the received read addresses;

a kernel memory coupled to receive the double buffered output information generated by the read access circuit, the kernel memory storing a kernel of information in response to the received double buffered output information; and

a kernel processor coupled to receive the kernel of information stored by the kernel memory, the kernel processor generating filtered output information in response to the received kernel of information.

38. A kernel processor system as set forth in claim 37, further comprising a display monitor coupled to receive filtered output information generated by the kernel processor, the display monitor displaying a filtered image in response to the received filtered output information.

39. A process of operating a kernel processor system comprising the acts of:

generating input information;

storing double buffered information in a double buffer memory;

generating write addresses;

writing the double buffered information into the double buffer memory in response to the input information and in response to the write addresses;

generating read addresses;

generating a plurality of lines of double buffered output information in response to the double buffered information stored in the double buffer memory and in response to the read addresses;

storing a kernel of information in response to the plurality of lines of double buffered output information; and

generating filtered output information in response to the kernel of information.

40. A process of operating a kernel processor system comprising the acts of:

generating input information;

storing double buffered information in a double buffer memory;

generating write addresses;

writing the double buffered information into the double buffer memory in response to the input information and in response to the write addresses;

generating read addresses;

generating a plurality of lines of double buffered output information in response to the double buffered information stored in the double buffer memory and in response to the read addresses;

storing a kernel of information in response to the plurality of lines of double buffered output information;

generating filtered output information in response to the kernel of information; and

making a product in response to the filtered output information.

41. A process of operating a kernel processor system comprising the acts of:

generating input information;

storing double buffered information in a double buffer memory;

generating write addresses;

writing the double buffered information into the double buffer memory in response to the input information and in response to the write addresses;

generating read addresses;

generating double buffered output information in response to the double buffered information stored in the double buffer memory and in response to the read addresses;

storing a kernel of information in response to the double buffered output information; and

generating filtered output information in response to the kernel of information.

42. A process of operating a kernel processor system comprising the acts of:

generating input information;

storing double buffered information in a double buffer memory;

generating write addresses;

writing the double buffered information into the double buffer memory in response to the input information and in response to the write addresses;

generating read addresses;

generating double buffered output information in response to the double buffered information stored in the double buffer memory and in response to the read addresses;

storing a kernel of information in response to the double buffered output information;

generating filtered output information in response to the kernel of information; and

making a product in response to the filtered output information.

43. A kernel processor system comprising:

an input circuit generating an input line of display information;

a first line buffer storing a first line of display information;

a second line buffer storing a second line of display information;

a third line buffer storing a third line of display information;

a writing circuit coupled to receive the input line of display information generated by the input circuit, the writing circuit writing the first line of display information into the first line buffer in response to the received input line of display information;

a double buffered control circuit coupled to receive the first line of display information stored by the first line buffer, coupled to receive the second line of display information stored by the second line buffer, and coupled to receive the third line of display information stored by the third line buffer;

the double buffered control circuit double buffering the first line of display information with the first line buffer, the second line buffer, and the third line buffer;

an output circuit coupled to the double buffered control circuit and generating a plurality of lines of double buffered display information in response to the double buffering of the first line of display information by the double buffer control circuit;

a kernel memory coupled to receive the plurality of lines of double buffered display information generated by the output circuit, the kernel memory storing a kernel of display information in response to the received plurality of lines of double buffered display information; and

a kernel processor coupled to the kernel memory and generating a line of spatially filtered display information in response to the kernel of display information stored by the kernel memory.

44. A kernel processor system comprising:

an input circuit generating input information;

a double buffer memory storing double buffered information;

a double buffered control circuit coupled to receive the input information generated by the input circuit and coupled to the double buffer memory, the double buffered control circuit double buffering the received input information in the double buffer memory and generating double buffered output information in response to the double buffered information stored by the double buffer memory;

a kernel memory coupled to receive double buffered output information generated by the double buffered control circuit, the kernel memory storing a kernel of information in response to the received double buffered output information; and

a kernel processor coupled to receive the kernel of information stored by the kernel memory, the kernel processor generating filtered output information in response to the received kernel of output information.