Apparatus for executing respective portions of a process by main and sub CPUS

• US 5,584,034 A
• Filed: 06/07/1995
• Issued: 12/10/1996
• Est. Priority Date: 06/29/1990
• Status: Expired due to Term

• Current Assignee: Casio Computer Company Limited
• Original Assignee: Casio Computer Company Limited
• Inventors: Akutsu, Takashi, Hosoda, Jun, Ogura, Kazuo, Jinbo, Teruo, Manabe, Hajime, Shiba, Kosuke, Yamaguchi, Yoshito, Daigo, Koichiro, Usami, Ryuji, Negoro, Yoshiki
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/486,606
• Time in Patent Office: 552 Days
• Field of Search: 395/182.1, 395/800, 395/200.05, 395/200.19, 395/288, 395/200.02, 395/306, 395/200.15, 395/200.18, 370/85.15, 84/602, 84/627, 84/644, 84/630, 364/DIG. 1, 364/DIG. 2, 364/132, 364/134, 379/88
• US Class Current: 712/35
• CPC Class Codes: G10H 2250/621 Waveform interpolation
• CPC Class Codes: G10H 7/004 with one or more auxiliary processor in addition to the main processing unit

Abstract

A main CPU and a sub CPU take share of executing a tone generating process to generate multiple tone signals on a real-time basis without using an exclusive tone generator. The main CPU and sub CPU are formed on a one-chip LSI, thus facilitating realization of a compact electronic musical instrument. According to another structure, the main CPU executes tone generation while the sub CPU performs an effect process, thereby permitting a one-chip LSI to generate an effect-added musical tone.

Claims

1. A digital information processing apparatus having a plurality of CPUs including one main CPU and at least one sub CPU to be controlled by said main CPU, said main CPU comprising:

MCPU program storage means for storing part of a process program for performing a predetermined process;

MCPU address control means for controlling an address of said MCPU program storage means;

MCPU data storage means for storing data necessary for said input process and said predetermined process;

MCPU arithmetic operation means coupled to said MCPU program storage means for executing an arithmetic operation; and

MCPU operation control means for decoding individual commands of said program stored in said MCPU program storage means and controlling operations of said MCPU address control means, said MCPU data storage means and said MCPU arithmetic operation means;

said at least one sub CPU comprising;

SCPU program storage means for storing a remaining portion of said process program for performing a predetermined process in association with said part of said process program stored in said MCPU program storage means;

SCPU address control means for controlling an address of said SCPU program storage means;

SCPU data storage means for storing data necessary for said predetermined process;

SCPU arithmetic operation means coupled to said SCPU program storage means for executing an arithmetic operation; and

SCPU operation control means for decoding individual commands of said program stored in said SCPU program storage means and controlling operations of said SCPU address control means, said SCPU data storage means and said SCPU arithmetic operation means; and

said digital information processing apparatus further comprising means for permitting said main CPU and sub CPU to execute respective portions of one predetermined process in accordance with said program.

2. A digital information processing apparatus having a plurality of CPUs including one main CPU and at least one sub CPU to be controlled by said main CPU, said main CPU comprising:

MCPU program storage means for storing an input processing program for executing an input process and a program for a first predetermined process to be executed based on a result of said input process;

MCPU address control means for controlling an address of said MCPU program storage means;

MCPU data storage means for storing data necessary for said input process and said first predetermined process;

MCPU arithmetic operation means coupled to said MCPU program storage means for executing an arithmetic operation; and

MCPU operation control means for decoding individual commands of said programs stored in said MCPU program storage means and controlling operations of said MCPU address control means, said MCPU data storage means and said MCPU arithmetic operation means;

said at least one sub CPU comprising;

SCPU program storage means for storing a process program for performing a second predetermined process on a result of said first predetermined process executed by said main CPU in accordance with said input process executed by said input processing program stored in said MCPU program storage means;

SCPU address control means for controlling an address of said SCPU program storage means;

SCPU data storage means for storing data necessary for said predetermined process;

SCPU arithmetic operation means coupled to said SCPU program storage means for executing an arithmetic operation; and

SCPU operation control means for decoding individual commands of said program stored in said SCPU program storage means and controlling operations of said SCPU address control means, said SCPU data storage means and said SCPU arithmetic operation means; and

said digital information processing apparatus further comprising means for permitting said main CPU and sub CPU to execute respective portions of one predetermined process in accordance with said program.