High performance peripheral interface with read-ahead capability
First Claim
1. A circuit for interfacing between a processor coupled to a computer bus and at least a first peripheral device interface, said circuit comprising:
- a read-ahead buffer coupled to the computer bus;
a data-in latch coupled between the read-ahead buffer and the first peripheral device interface;
a data-out latch coupled between the computer bus and the first peripheral device interface;
a controlling state machine coupled to said computer bus, said controlling state machine detecting peripheral device commands issued by said processor on the computer bus and providing a plurality of control signals for the read-ahead buffer, the data-in latch and the data-out latch; and
a read-ahead counter coupled to the controlling state machine for counting a plurality of input data words from the first peripheral device interface; and
a configuration register coupled to the controlling state machine,wherein said controlling state machine provides;
control signals to read a nth datum from said first peripheral device interface before said circuit detects a peripheral device command issued by said processor requesting said nth datum, said nth datum having an address that is adjacent to an address of the n-1th datum that said circuit for interfacing has read from said first peripheral device interface, wherein said n-1th datum is written from said read-ahead buffer into a memory of said processor while said nth datum is read from said first peripheral device interface into said data-in latch wherein said processor can perform other functions while said interface circuit is reading said nth datum from said first peripheral device interface, andcontrol signals to transfer an output datum stored in the data-out latch to the first peripheral device interface at least partially while said circuit is transferring an output datum from the computer bus to the data-out latch.
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Accused Products
Abstract
A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. The LBPI is coupled between the computer local bus and the peripheral interface(s) and has a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. The LPBI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active.
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Citations
61 Claims
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1. A circuit for interfacing between a processor coupled to a computer bus and at least a first peripheral device interface, said circuit comprising:
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a read-ahead buffer coupled to the computer bus; a data-in latch coupled between the read-ahead buffer and the first peripheral device interface; a data-out latch coupled between the computer bus and the first peripheral device interface; a controlling state machine coupled to said computer bus, said controlling state machine detecting peripheral device commands issued by said processor on the computer bus and providing a plurality of control signals for the read-ahead buffer, the data-in latch and the data-out latch; and a read-ahead counter coupled to the controlling state machine for counting a plurality of input data words from the first peripheral device interface; and a configuration register coupled to the controlling state machine, wherein said controlling state machine provides; control signals to read a nth datum from said first peripheral device interface before said circuit detects a peripheral device command issued by said processor requesting said nth datum, said nth datum having an address that is adjacent to an address of the n-1th datum that said circuit for interfacing has read from said first peripheral device interface, wherein said n-1th datum is written from said read-ahead buffer into a memory of said processor while said nth datum is read from said first peripheral device interface into said data-in latch wherein said processor can perform other functions while said interface circuit is reading said nth datum from said first peripheral device interface, and control signals to transfer an output datum stored in the data-out latch to the first peripheral device interface at least partially while said circuit is transferring an output datum from the computer bus to the data-out latch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An interface circuit for transferring information between a processor coupled to a computer bus and at least a first peripheral device interface, said circuit comprising:
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a read buffer coupled between the computer bus and the first peripheral device interface for storing input data received from the first peripheral device interface and for transferring the input data to the computer bus; a write buffer coupled between the computer bus and the first peripheral device interface for storing output data received from the computer bus and transferring the output data to the first peripheral device interface; and a controlling state machine coupled to the computer bus, to said read buffer and said write buffer, said controlling state machine detecting peripheral device commands issued by said processor from the computer bus and in response to said peripheral device commands provides a plurality of control signals to said write buffer and said read buffer for storing and transferring of the output data and input data respectively, wherein the controlling state machine provides control signals to said read buffer and the first peripheral device interface to read a nth datum from the first peripheral device interface before said interface circuit detects a peripheral device command issued by said processor requesting said nth datum, said nth datum having an address that is adjacent to an address of a n-1th datum that said interface circuit has read from said first peripheral device interface, wherein said n-1th datum is written from said read buffer into a memory of said processor while said nth datum is read from said first peripheral device interface into said read buffer, wherein said processor can perform other functions while said interface circuit is reading said nth datum from said first peripheral device interface. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A circuit for interfacing between a processor coupled to a computer bus and at least a first peripheral device interface, said circuit comprising:
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a first means for buffering coupled between the computer bus and the first peripheral device interface for storing input data received from the first peripheral device interface and for transferring the input data to the computer bus; a second means for buffering coupled between the computer bus and the first peripheral device interface for storing output data received from the computer bus and for transferring the output data to the first peripheral device interface; and means, coupled to said computer bus, to said first buffering means and to said second buffering means, for controlling said storing and transferring of the input data to read a nth datum from the first peripheral device interface before said interface circuit detects a peripheral device command issued by said processor requesting said nth datum, said nth datum having an address that is adjacent to an address of the n-1th datum that said interface circuit has read from said first peripheral device interface, wherein said n-1th datum is written from said first means for buffering into a memory of said processor while said nth datum is read from said first peripheral device interface into said first means for buffering, wherein said processor can perform other functions while said interface circuit is reading said nth datum from said first peripheral device interface. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61)
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Specification