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High performance peripheral interface with read-ahead capability

  • US 5,584,040 A
  • Filed: 10/30/1995
  • Issued: 12/10/1996
  • Est. Priority Date: 10/20/1992
  • Status: Expired due to Term
First Claim
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1. A circuit for interfacing between a processor coupled to a computer bus and at least a first peripheral device interface, said circuit comprising:

  • a read-ahead buffer coupled to the computer bus;

    a data-in latch coupled between the read-ahead buffer and the first peripheral device interface;

    a data-out latch coupled between the computer bus and the first peripheral device interface;

    a controlling state machine coupled to said computer bus, said controlling state machine detecting peripheral device commands issued by said processor on the computer bus and providing a plurality of control signals for the read-ahead buffer, the data-in latch and the data-out latch; and

    a read-ahead counter coupled to the controlling state machine for counting a plurality of input data words from the first peripheral device interface; and

    a configuration register coupled to the controlling state machine,wherein said controlling state machine provides;

    control signals to read a nth datum from said first peripheral device interface before said circuit detects a peripheral device command issued by said processor requesting said nth datum, said nth datum having an address that is adjacent to an address of the n-1th datum that said circuit for interfacing has read from said first peripheral device interface, wherein said n-1th datum is written from said read-ahead buffer into a memory of said processor while said nth datum is read from said first peripheral device interface into said data-in latch wherein said processor can perform other functions while said interface circuit is reading said nth datum from said first peripheral device interface, andcontrol signals to transfer an output datum stored in the data-out latch to the first peripheral device interface at least partially while said circuit is transferring an output datum from the computer bus to the data-out latch.

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