Multi-stage digital to analog conversion circuit and method

• US 5,585,802 A
• Filed: 11/02/1994
• Issued: 12/17/1996
• Est. Priority Date: 11/02/1994
• Status: Expired due to Term

• Current Assignee: Microsemi Semiconductor (U.S.) Inc. (Microchip Technology Incorporated)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cabler, Carlin D., Linz, Alfredo R.
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US08/333,460
• Time in Patent Office: 776 Days
• Field of Search: 341/61, 341/143, 341/144, 341/152, 364/724.1, 377/42, 377/48, 377/76
• US Class Current: 341/144
• CPC Class Codes: G06F 3/162 Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
• CPC Class Codes: G10H 1/0066 using a MIDI interface
• CPC Class Codes: G10H 1/125 using a digital filter
• CPC Class Codes: G10H 2230/035 Power management, i.e. specific power supply solutions for electrophonic musical instruments, e.g. auto power shut-off, energy saving designs, power conditioning, connector design, avoiding inconvenient wiring
• CPC Class Codes: G10H 2240/311 MIDI transmission G10H2240/056 takes precedence
• CPC Class Codes: G10H 2250/191 Chebyshev polynomials, e.g. to provide filter coefficients for sharp rolloff filters Chebyshev filters G10H2250/091; Chebyshev windows G10H2250/271
• CPC Class Codes: G10H 2250/545 Aliasing, i.e. preventing, eliminating or deliberately using aliasing noise, distortions or artifacts in sampled or synthesised waveforms, e.g. by band limiting, oversampling or undersampling, respectively
• CPC Class Codes: G10H 2250/571 Waveform compression, adapted for music synthesisers, sound banks or wavetables audio compression G10L19/00
• CPC Class Codes: G10H 2250/611 Waveform decimation, i.e. integer division of the sampling rate for reducing the number of samples in a discrete-time signal, e.g. by low-pass anti-alias filtering followed by the actual downsampling
• CPC Class Codes: G10H 7/002 using a common processing for different operations or calculations, and a set of microinstructions (programme) to control the sequence thereof
• CPC Class Codes: H03K 23/68 with a base which is a non-integer
• CPC Class Codes: H03M 3/504 the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC
• CPC Class Codes: H03M 3/508 Details relating to the interpolation process

Abstract

This invention is for a digital-to-analog conversion circuit (DAC) which includes an interpolation filter circuit, a noise shaper circuit and a semi-digital FIR filter circuit. The entire DAC circuit provides noise shaping, analog filtering and oversampling functions.

Claims

1. A digital-to-analog conversion (DAC) circuit, comprising:

(a) an multi-stage interpolation filter circuit, having a multi-bit input and a multi-bit output;

(b) a noise shaper circuit, having a multi-bit input and a 1-bit output, said noise shaper input being connected to said multi-bit output from said multi-stage interpolation filter circuit; and

(c) a semi-digital FIR filter circuit, having a digital input and an analog output, with said FIR filter digital input being connected to said 1-bit output from said noise shaper circuit, wherein said FIR filter circuit further comprises a shift register having output taps and an input, said shift register input being connected to said FIR filter digital input, a plurality of current sinks, a plurality of DC offset current sources and a first and a second current summing operational amplifier, wherein said current sinks and DC offset current sources are selectively connected to inputs to said first and second current summing operational amplifiers and wherein said inputs of said first and second current summing operational amplifiers are also selectively connected to said output taps of said shift register.

2. The DAC circuit of claim 1, wherein a first stage of said multi-stage interpolation filter comprises a linear phase FIR filter having an input, an output and 2N-1 taps, whereby said first stage oversamples the frequency of a digital audio signal input to said first stage to twice the sample rate of said digital audio input signal.

3. The DAC circuit of claim 2, wherein a second stage of said multi-stage interpolation filter comprises a two-phase sinc⁵ interpolation second stage having an input and an output where said second stage input is connected to said output of said first interpolation stage, and whereby said sinc⁵ stage oversamples said output of said first interpolation stage to four times the sample rate of said digital audio signal input to said first interpolation stage, wherein said input of said second stage is connected to a first multiplier and to a first delay block, and wherein the output of said first delay block is input to a second delay block and to a second multiplier and, wherein the output of said second delay block is input to a third multiplier, wherein said first multiplier is within a first processing path, said second multiplier is within a second processing path and said third multiplier is within a third processing path, wherein said first, second and third processing paths operate in parallel, and wherein the output of said first processing path is summed with the output of said second processing path in a first summing node, and wherein the output of said third processing path and the output of said second processing path are summed in a second summing node, wherein an oversampler at the output of said second stage selectively samples between the output of said first summing node and said second summing node and outputs the sample so selected to said output of said second stage.

4. The DAC circuit of claim 3, wherein a third stage of said multi-stage interpolation filter comprises a sinc² interpolation third stage having an input and an output, where said third stage output is connected to said output of said sinc⁵ second stage, whereby said sinc² third stage oversamples said output of said sinc⁵ stage to 64 times the sample rate of said digital audio signal input to said first interpolation stage, wherein said third stage input is input to a double delay block and input to a first summing node, wherein the output of said double delay block is input to said first summing node as a negative input, wherein an output of said first summing node is input to a first single delay block and input to a second summing node, wherein the output of said first single delay block is input to said second summing node, and wherein an output of said second summing node is connected to an oversampler, wherein said oversampler selectively samples the output of said second summing node and inputs each said sample selected to an input of a third summing node at 16 times the clock rate of said third summing node, wherein an output of said third summing node is input to a second single delay block, wherein the output of said second single delay block is fed back to an input of said third summing node and is also output from said third stage as a 64 times oversampled signal.

5. The DAC circuit of claim 2, wherein said linear phase FIR filter first stage further comprises a two-phase filter, wherein a first phase sub-filter generates odd signal samples by multiplying said digital audio input signal by odd coefficients and wherein a second phase sub-filter generates even signal samples by multiplying said digital audio input signal by even coefficients, whereby said sub-filters execute in parallel.

6. The DAC circuit of claim 1, wherein said noise shaper circuit comprises a 5th order sigma-delta modulator.

7. The DAC circuit of claim 6, wherein said 5th order sigma-delta modulator has a signal transfer function of:

##EQU31## where X(z) is the digital audio input signal, whereby ##EQU32## W₅ =-A₅ K₅, wherein A_1-5 are pole positioning feedback coefficients, B_1-2 are zero positioning feedback coefficients, and K_1-5 are scaling factors.

8. The DAC circuit of claim 6, wherein said 5th order sigma-delta modulator has a noise transfer function of:

##EQU33## whereby ##EQU34## W₅ =-A₅ K₅, wherein A_1-5 are pole positioning feedback coefficients, B_1-2 are zero positioning feedback coefficients, and K_1-5 are scaling factors.

9. The DAC circuit of claim 1, wherein said noise shaper circuit extends the noise stop band to at least about 0.70 f_s.

10. The DAC circuit of claim 1, wherein said noise shaper circuit extends the noise stop band of said noise shaper circuit to about 0.75 f_s.

11. The DAC circuit of claim 1, wherein said noise shaper circuit comprises a fifth order sigma-delta network having five integrators, whereby scaling coefficients for two of said integrators are the same value as scaling coefficients for two other of said integrators.

12. The DAC circuit of claim 1, wherein said noise shaper circuit includes a fifth order sigma-delta network having a noise gain factor (K) of less than about 1.85.

13. The DAC circuit of claim 1, wherein said semi-digital FIR filter comprises:

(a) a shift register having a clock input, a 1-bit digital audio signal input and a plurality of data output taps;

(b) a plurality of current sinks;

(c) a plurality of DC offset current sources;

(d) a first and a second current summing operational amplifier, wherein each said current summing operational amplifier has a voltage output node and a positive and a negative input node, wherein said negative input node for each said current summing operational amplifier is a current summing input node which is connected to a different one of said DC offset current sources and is selectively connected to either said current sinks, and said positive input node for each said current summing operational amplifier is connected to a reference voltage, and wherein a first resistor is connected between said current summing node and said voltage output node on said first current summing operational amplifier, and wherein a second resistor is connected between said current summing node and said voltage output node on said second current summing operational amplifier, and wherein the voltage on said voltage output node on each said current summing operational amplifier is related to the value of said current sinks selectively connected to said current summing node for each said current summing operational amplifier; and

(e) an operational amplifier, having a single ended voltage output node and a positive and a negative voltage input node, wherein said negative voltage input node is connected through a third resistor to the voltage output node of said first or second current summing operational amplifier and said positive voltage input node is connected through a fourth resistor to the voltage output node of said other current summing operational amplifier, and a fifth resistor is connected to a reference voltage and to said positive voltage input node of said operational amplifier, and wherein a sixth resistor is connected between said negative voltage input node and said single ended voltage output node, whereby the voltage on said single ended voltage output node is related to the value of said current sinks selectively connected to said current summing node for each said current summing operational amplifier.

14. The DAC circuit of claim 13, wherein a first capacitor is connected in parallel with said first resistor and a second capacitor is connected in parallel with said second resistor.

15. A method of converting an n-bit digital signal to an analog signal, comprising the steps off

(a) inputting said n-bit signal to a multi-stage interpolator filter circuit;

(b) interpolating said input n-bit digital signal to 64 times the sample rate of said n-bit signal;

(c) outputting said interpolated signal to a noise shaper circuit;

(d) converting said interpolated signal to a 1-bit output signal;

(e) inputting said 1-bit output signal to a semi-digital FIR filter circuit, wherein said FIR filter circuit comprises a shift register having output taps and an input, said shift register input being connected to said FIR filter digital input, a plurality of current sinks, a plurality of DC offset current sources and a first and a second current summing operational amplifier, wherein said current sinks and DC offset current sources are selectively connected to inputs to said first and second current summing operational amplifiers and wherein said inputs of said first and second current summing operational amplifiers are also selectively connected to said output taps of said shift register; and

(f) converting said 1-bit signal to an analog output signal.

16. A method of converting an n-bit digital audio signal to an analog audio signal, comprising the steps of:

(a) inputting said n-bit audio signal to a three-stage interpolator filter circuit;

(b) interpolating said input n-bit digital signal in a first stage interpolator circuit to twice the sample rate of said n-bit digital audio signal;

(c) outputting said first stage interpolated signal to a second stage interpolator circuit;

(d) interpolating said first stage interpolated signal to four times the sample rate of said n-bit digital audio signal;

(e) outputting said second stage interpolated signal to a third stage interpolator circuit;

(f) interpolating said second stage interpolated signal to 64 times the sample rate of said n-bit digital audio signal;

(g) outputting said third stage interpolated signal to a 1-bit noise shaper circuit;

(h) converting said third stage interpolated signal to a 1-bit signal;

(i) outputting said 1-bit signal to a semi-digital FIR filter circuit, wherein said FIR filter circuit comprises a shift register having output taps and an input, said shift register input being connected to said FIR filter digital input, a plurality of current sinks, a plurality of DC offset current sources and a first and a second current summing operational amplifier, wherein said current sinks and DC offset current sources are selectively connected to inputs to said first and second current summing operational amplifiers and wherein said inputs of said first and second current summing operational amplifiers are also selectively connected to said output taps of said shift register; and

(j) converting said 1-bit signal to an analog audio output signal.

17. The method of claim 16, wherein said first stage interpolator circuit comprises a linear phase FIR filter.

18. The method of claim 16, wherein said second stage interpolator circuit comprises a sinc⁵ filter.

19. The method of claim 16, wherein said third stage interpolator circuit comprises a sinc² filter.

20. The method of claim 16, further comprising the step of:

(k) low pass filtering said analog audio output signal.