Equalization for sample value estimation and sequence detection in a sampled amplitude read channel

• US 5,585,975 A
• Filed: 11/17/1994
• Issued: 12/17/1996
• Est. Priority Date: 11/17/1994
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Bliss, William G.
• Primary Examiner(s): Psitos, Aristotelis
• Assistant Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US08/340,993
• Time in Patent Office: 761 Days
• Field of Search: 360/65, 360/40, 360/66, 360/67, 360/22, 360/24, 360/51, 341/59, 364/602, 375/290, 375/340, 375/345, 375/376, 375/355
• US Class Current: 360/65
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10037 A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
• CPC Class Codes: G11B 20/10055 using partial response filtering when writing the signal to the medium or reading it therefrom
• CPC Class Codes: G11B 20/10064 EEPR4 or E2PR4, i.e. extended partial response class 4, polynomial (1-D)*(1+D)3
• CPC Class Codes: G11B 20/10074 EPR4, i.e. extended partial response class 4, polynomial (1-D) *(1+D)2

Abstract

In a sampled amplitude magnetic read channel, pulses in an analog signal corresponding to flux transitions on a magnetic medium are sampled and equalized into a first equalization for estimating sample values and into a second equalization for sequence detection of digital data. A gain and phase error detector generate respective error signals corresponding to the difference between estimated and actual sample values. Gain control and timing recovery use the error signals to adjust the amplitude and sampling frequency/phase of the analog read signal. A pair of programmable discrete time filters equalize the signal samples into the desired equalization. In a first embodiment, the signal samples are equalized to PR4 for estimating sample values and to EPR4 for sequence detection. A slicer processes the PR4 equalized sample values to generate the estimated sample values. The gain and phase error detectors generate the corresponding error signals according to a minimum mean squared error stochastic gradient algorithm. In a second embodiment, the signal samples are equalized to EPR4 for estimating sample values and to EEPR4 for sequence detection. A pulse detector processes the EPR4 equalized sample values in order to detect pulses in the analog signal and generate a corresponding pulse detect signal. The gain and phase error detectors generate the corresponding error signals in response to the pulse detect signal. To minimize circuitry and associated cost, the discrete time equalizing filters are implemented in series. For d=1 recording, the second equalizing filter is a (1+D) notch filter that attenuates the noise caused by clocking the discrete time circuitry at half the sampling rate, thereby increasing the accuracy of the sequence detector.

Claims

1. A sampled amplitude read channel for reading digital data from a magnetic medium by detecting the digital data from a sequence of discrete time sample values generated by sampling pulses in an analog signal from a magnetic read head positioned over the magnetic medium, said sampled amplitude read channel comprising:

(a) a first discrete time equalizing filter, responsive to the discrete time sample values, for filtering the discrete time sample values into a predetermined first equalization and outputting first equalized sample values;

(b) a second discrete time equalizing filter, responsive to the discrete time sample values, for filtering the discrete time sample values into a predetermined second equalization and outputting second equalized sample values;

(c) a sample value processor, connected to receive the first equalized sample values, for generating a control signal;

(d) an error detector, connected to receive the control signal and the first equalized sample values, for generating an error signal; and

(e) a discrete time sequence detector, connected to receive the second equalized sample values, for detecting the digital data.

2. The sampled amplitude read channel as recited in claim 1, wherein:

(a) the first discrete time equalizing filter equalizes the discrete time sample values into a PR4 equalization; and

(b) the second discrete time equalizing filter equalizes the discrete time sample values into an equalization selected from the group consisting of EPR4 and EEPR4.

3. The sampled amplitude read channel as recited in claim 1, wherein d=0.

4. The sampled amplitude read channel as recited in claim 1, wherein the first discrete time equalizing filter comprises programmable coefficients programmed to generate the first equalization.

5. The sampled amplitude read channel as recited in claim 1, wherein the second discrete time equalizing filter comprises programmable coefficients programmed to generate the second equalization.

6. The sampled amplitude read channel as recited in claim 1, wherein the first and second discrete time equalizing filters are connected in series.

7. The sampled amplitude read channel as recited in claim 1, wherein:

(a) the sampling of the analog signal occurs at a predetermined sampling frequency;

(b) the discrete time sequence detector is clocked at half the sampling frequency; and

(c) the second discrete time equalizing filter is a notch filter for attenuating a noise signal in the discrete time sample values associated with clocking the sequence detector at half the sampling frequency.

8. The sampled amplitude read channel as recited in claim 1, wherein the sample value processor is a slicer for generating estimated sample values X(n) according to the following table:

space="preserve" listing-type="tabular">______________________________________ sample value slicer output ______________________________________ y >

= T1 +M -T2 <

= y <

T1 0 y <

-T2 -M ______________________________________

wherein;

(a) y are the first equalized sample values;

(b) T1 and T2 are predetermined thresholds; and

(c) M is a magnitude of the estimated sample values X(n).

9. The sampled amplitude read channel as recited in claim 8, wherein said predetermined thresholds T1 and T2 are programmable.

10. The sample amplitude read channel as recited in claim 8, further comprising timing control for synchronizing the sampling of the pulses, wherein:

(a) the error detector is a phase error detector and the error signal is a phase error Δ

t(n); and

(b) the phase error Δ

t(n) is proportional to;

space="preserve" listing-type="equation">(Y(n-1)*X(n))-(Y(n)*X(n-1))

wherein Y(n) are the first equalized sample values.

11. The sampled amplitude read channel as recited in claim 8, further comprising gain control for adjusting the amplitude of the analog signal, wherein:

(a) the error detector is a gain error detector and the error signal is a gain error Δ

g(n); and

(b) said gain error Δ

g(n) is proportional to;

space="preserve" listing-type="equation">(Y(n)-x(n))*X(n)

wherein Y(n) are the first equalized sample values.

12. The sampled amplitude read channel as recited in claim 1, wherein the sample value processor is a pulse detector for detecting pulses in the analog signal and outputting a pulse signal Pn.

13. The sampled amplitude read channel as recited in claim 12, wherein:

(a) the first discrete time equalizing filter equalizes the sample values into an EPR4 equalization; and

(b) the second discrete time equalizing filter equalizes the sample values into an EEPR4 equalization.

14. The sampled amplitude read channel as recited in claim 12, further comprising timing recovery for synchronizing the sampling of the pulses, wherein:

(a) the error detector is a phase error detector and the error signal is a phase error Δ

t(n);

(b) the read channel operates in an acquisition and tracking mode;

(c) when the read channel is in acquisition mode, the phase error Δ

t(n) is proportional to;

space="preserve" listing-type="equation">Pn*[SGN(Y(n-1))*(Y(n-2)-Y(n-1))+ta];

(d) when the read channel is in tracking mode, the phase error Δ

t(n) is proportional to;

space="preserve" listing-type="equation">Pn*[SGN(Y(n-1))*(Y(n-2)-Y(n-1))+tt+c*Pn-2-a*Pn+2];

(e) Y(n) are the first equalized sample values;

(f) a and c are predetermined constants;

(g) SGN(x) is +1 for x>

=0 and -1 for x<

0;

(h) ta is a predetermined acquisition timing set point; and

(i) tt is a predetermined tracking timing set point.

15. The sampled amplitude read channel as recited in claim 12, further comprising timing recovery for synchronizing the sampling of the pulses, wherein:

(a) the error detector is a phase error detector and the error signal is a phase error Δ

t(n);

(b) the read channel operates in an acquisition and tracking mode;

(c) when the read channel is in acquisition mode, the phase error Δ

t(n) is proportional to;

space="preserve" listing-type="equation">Pn*[SGN(Y(n-1))*(Y(n-2)-Y(n))+ta];

(d) when the read channel is in tracking mode, the phase error Δ

t(n) is proportional to;

space="preserve" listing-type="equation">Pn*[SGN(Y(n-1))*(Y(n-2)-Y(n))+tt+c*Pn-2-b*Pn+2-a*Pn-3];

(e) Y(n) are the second equalized sample values;

(f) a, b and c are predetermined constants;

(g) SGN(x) is +1 for x>

=0 and -1 for x<

0;

(h) ta is a predetermined acquisition timing set point; and

(i) tt is a predetermined tracking timing set point.

16. The synchronous read channel as recited in claim 12, further comprising gain control for adjusting the amplitude of the analog signal, wherein:

(a) the error detector is a gain error detector and the error signal is a gain error Δ

g; and

(b) the read channel operates in an acquisition and tracking mode;

(c) when the read channel is in acquisition mode, the gain error Δ

g is proportional to;

space="preserve" listing-type="equation">Pn*[-SGN(Y(n-1))*(Y(n-1)+Y(n-2))+ga-(a+c)Pn-2];

(d) when the read channel is in tracking mode, the gain error Δ

g(n) is proportional to;

space="preserve" listing-type="equation">Pn*[-SGN(Y(n-1))*(Y(n-1)+Y(n-2))+gt-(a+c)Pn-2];

(e) Y(n) are the first equalized sample values;

(f) a and c are predetermined constants;

(g) SGN(x) is +1 for x>

=0 and -1 for x<

0;

(h) ga is a predetermined acquisition gain set point; and

(i) gt is a predetermined tracking gain set point.

17. The synchronous read channel as recited in claim 12, further comprising gain control for adjusting the amplitude of the analog signal, wherein:

(a) the error detector is a gain error detector and the error signal is a gain error Δ

g; and

(b) the read channel operates in an acquisition and tracking mode;

(c) when the read channel is in acquisition mode, the gain error Δ

g is proportional to;

space="preserve" listing-type="equation">Pn[-SGN(Y(n-1))*(Y(n-1))+ga-a*Pn-2];

(d) when the read channel is in tracking mode, the gain error Δ

g(n) is proportional to;

space="preserve" listing-type="equation">Pn[-SGN(Y(n-1))*(Y(n-1))+gt-a*Pn-2];

(e) Y(n) are the second equalized sample values;

(f) a is a predetermined constant;

(g) SGN(x) is +1 for x>

=0 and -1 for x<

0;

(h) ga is a predetermined acquisition gain set point; and

(i) gt is a predetermined tracking gain set point.

18. The sampled amplitude read channel as recited in claim 12, wherein said pulse detector operates according to the following table:

space="preserve" listing-type="tabular">__________________________________________________________________________ Acquisition Tracking __________________________________________________________________________SGN(Y(n -

     1))) = +1 Y(n -

     1) >

Y(n);

Y(n -

     1) >

Y(n);

(positive pulse) Y(n -

     1) >

Y(n -

     2);

Y(n -

     1) >

Y(n -

     2);

Y(n -

     2) >

Y(n -

     3) Y(n -

     2) >

V SGN(Y(n -

     1)) = -1 Y(n -

     1) <

Y(n);

Y(n -

     1) <

Y(n);

(negative pulse) Y(n -

     1) <

Y(n -

     2);

Y(n -

     1) <

Y(n -

     2);

Y(n -

     2) <

Y(n -

     3) Y(n -

     2) <

-V __________________________________________________________________________

wherein;

(a) the read channel operates in an acquisition and tracking mode;

(b) SGN(x) is -1 if x<

0, and SGN(x) is +1 if x>

=0; and

(c) V and -V are predetermined thresholds.

19. The sampled amplitude read channel as recited in claim 18, wherein the predetermined thresholds V and -V are programmable.

20. The sampled amplitude read channel as recited in claim 12, wherein said pulse detector operates according to the following table:

space="preserve" listing-type="tabular">__________________________________________________________________________ Acquisition Tracking __________________________________________________________________________SGN(Y(n -

     1))) = +1 SGN(Z(n)) = Y(n -

     1) >

V;

(positive pulse) SGN(Z(n -

     1));

Y(n -

     1) >

Y(n -

     2);

SGN(Z(n -

     1)) != Y(n -

     1) >

Y(n) SGN(Z(n -

     2)) SGN(Y(n -

     1)) = -1 SGN(Z(n)) = Y(n -

     1) <

-V;

(negative pulse) SGN(Z(n -

     1));

Y(n -

     1) <

Y(n -

     2);

SGN(Z(n -

     1)) != Y(n -

     1) <

Y(n) SGN(Z(n -

     2)) __________________________________________________________________________

wherein;

(a) the read channel operates in an acquisition and tracking mode;

(b) z(n)=(Y(n)+Y(n-1))/2;

(c) SGN(x) is -1 if x<

0, and SGN(x) is +1 if x>

=0; and

(d) V and -V are predetermined thresholds.

21. The synchronous read channel as recited in claim 20, wherein the predetermined thresholds V and -V are programmable.

22. A sampled amplitude read channel for reading digital data from a magnetic medium by detecting the digital data from a sequence of discrete time sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium, said sampled amplitude read channel comprising:

(a) a first equalizing filter, responsive to the analog read signal, for generating a first equalized read signal;

(b) a second equalizing filter, responsive to the analog read signal, for generating a second equalized read signal;

(c) a sample value processor, connected to receive the first equalized read signal, for generating a control signal;

(d) an error detector, connected to receive the control signal and the first equalized read signal, for generating an error signal; and

(e) a discrete time sequence detector, connected to receive the second equalized read signal, for detecting the digital data.

23. The sampled amplitude read channel as recited in claim 22, wherein the sample value processor is a sample value estimator for generating estimated sample values X(n).

24. The sampled amplitude read channel as recited in claim 22, wherein the sample value processor is a pulse detector for generating a pulse detected signal Pn.

25. The sampled amplitude read channel as recited in claim 22, further comprising timing recovery, responsive to the error signal, for synchronizing the sampling of the analog read signal.

26. The sampled amplitude read channel as recited in claim 22, further comprising automatic gain control, responsive to the error signal, for adjusting the amplitude of the analog read signal.

27. The sampled amplitude read channel as recited in claim 22, wherein:

(a) the first equalized read signal is equalized according to a PR4 equalization; and

(b) the second equalized read signal is equalized according to an equalization selected from the group consisting of EPR4 and EEPR4.

28. The sampled amplitude read channel as recited in claim 22, wherein:

(a) the first equalized read signal is equalized according to a EPR4 equalization; and

(b) the second equalized read signal is equalized according to a EEPR4 equalization.

29. The sampled amplitude read channel as recited in claim 22, wherein the first and second equalizing filters are connected in series.