Arithmetic logic unit with zero sum prediction

• US 5,586,069 A
• Filed: 09/30/1994
• Issued: 12/17/1996
• Est. Priority Date: 09/30/1994
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Dockser, Kenneth A.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/315,465
• Time in Patent Office: 809 Days
• Field of Search: 364/736.5, 364/736, 364/786
• US Class Current: 708/525
• CPC Class Codes: G06F 7/02 Comparing digital values G06F7/06, G06F7/22, G06F7/38 take precedence
• CPC Class Codes: G06F 7/49905 Exception handling
• CPC Class Codes: G06F 7/505 in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/3001 Arithmetic instructions

Abstract

An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition for performance of the second operation. Instead of performing zero detection on the result, zero prediction is performed on the initial or intermediate operands, (e.g., partial products that are summed to generate a product). To this end, zero-prediction logic determines whether or not both of the following conditions are met: 1) either the least significant bits of the addends are the same and the carry-in is zero or the least significant bits of the addends are different and the carry-in is one. 2) for each pair of adjacent bit positions, the four included bits are consistent with addend complementarity. If both conditions are met, a zero result is predicted; otherwise, a non-zero result is predicted.

Claims

1. An arithmetic logic unit comprising:

operand register means for storing first and second operands and a carry-in;

result register means for storing a result and a one-bit zero indication of whether or not said result is zero;

operating means for applying an operation to said first and second operands so as to obtain said result, said operating means being coupled to said operand register means for receiving said first and second operands therefrom, said operating means being coupled to said result register means for providing said result thereto, said operating means includes an adder for providing said result as a sum of said operands and said carry-in; and

zero-prediction means for determining whether or not said result is to be zero by the time said result is obtained by said operating means, said zero-prediction means being coupled to said operand register means for receiving said operands therefrom, said zero-prediction means being coupled to said result register means for providing said zero indication thereto, said zero-prediction means including zero-prediction logic for determining whether or not said operands are two'"'"'s complements, said zero-prediction means determining whether or not said operands are one'"'"'s complements when said carry in is one, said zero-prediction logic having an addition mode and a subtraction mode, said zero-prediction logic including an AND gate means for providing said zero indication to said result register means, said AND gate means having plural inputs, at least one of said plural inputs while said zero-prediction logic is in said addition mode being coupled to sublogic implementing the function (A_n XNOR B_n) XOR (A_n-1 OR B_n-1), where A_n is the nth least significant bit of said first operand, A_n-1 is the (n-1)st least significant bit of said first operand, B_n is the nth least significant bit of said second operand, and B_n-1 is the (n-1)st least significant bit of said second operand, where n>

1.