Semiconductor device having a multi-layer channel structure
First Claim
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1. A non-volatile semiconductor memory device comprising:
- a semiconductor substrate of one conductivity type;
a memory cell with respect to which at least the data writing operation can be effected and which includes a threshold variable type transistor including a channel region having one surface and provided in said semiconductor substrate, a gate insulation film provided on said one surface of said channel region, a gate provided on said gate insulation film, and a charge storage layer provided in said gate insulation film;
gate potential supplying means for supplying a readout potential to said gate at the time of data readout operation and supplying a writing potential higher than the readout potential to said gate at the time of data writing operation;
a surface channel layer provided in contact with said one surface in said channel region, the conductivity type thereof being inverted only when the writing potential is applied to said gate; and
a buried channel layer provided in contact with said surface channel layer in said channel region, the conductivity type thereof being inverted when one of the readout potential and the writing potential is applied to said gate.
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Abstract
A non-volatile semiconductor memory cell has a channel layer with a two-layered structure including a surface channel layer and a buried channel layer. The operation of reading out "1" level data or "0" level data from the memory cell is effected by using only the buried channel layer and based on whether the conductivity type of the buried layer is inverted or not. The operation of writing "0" level data is effected by using both of the surface channel layer and the buried channel layer, simultaneously inverting the conductivity types of the surface channel layer and the buried channel layer, and passing a current into the inverted layer to generate hot electrons.
72 Citations
89 Claims
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1. A non-volatile semiconductor memory device comprising:
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a semiconductor substrate of one conductivity type; a memory cell with respect to which at least the data writing operation can be effected and which includes a threshold variable type transistor including a channel region having one surface and provided in said semiconductor substrate, a gate insulation film provided on said one surface of said channel region, a gate provided on said gate insulation film, and a charge storage layer provided in said gate insulation film; gate potential supplying means for supplying a readout potential to said gate at the time of data readout operation and supplying a writing potential higher than the readout potential to said gate at the time of data writing operation; a surface channel layer provided in contact with said one surface in said channel region, the conductivity type thereof being inverted only when the writing potential is applied to said gate; and a buried channel layer provided in contact with said surface channel layer in said channel region, the conductivity type thereof being inverted when one of the readout potential and the writing potential is applied to said gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A non-volatile semiconductor memory device comprising:
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a semiconductor substrate of a first conductivity type; a first memory cell with respect to which at least the data writing operation can be effected and which includes a threshold variable type transistor including a channel region having one surface and provided in said semiconductor substrate, a gate insulation film provided on said one surface of said channel region, a gate provided on said gate insulation film, a charge storage layer provided in said gate insulation film, a first terminal region of a second conductivity type provided in contact with said channel region in said substrate, and a second terminal region of said second conductivity type connected to a source and provided in contact with said channel region in said substrate; a second memory cell with respect to which at least the data writing operation can be effected and which includes a threshold variable type transistor including a channel region having one surface and provided in said semiconductor substrate, a gate insulation film provided on said one surface of said channel region, a gate provided on said gate insulation film, a charge storage layer provided in said gate insulation film, a first terminal region of said second conductivity type provided in contact with said channel region in said substrate and connected to said first terminal region of said first memory cell, and a second terminal region of said second conductivity type connected to a drain and provided in contact with said channel region in said substrate; gate potential supplying means for supplying a readout conduction potential to one of said gates of said first and second memory cells and supplying a selection readout potential to the other gate at the time of data readout operation and supplying a writing conduction potential higher than the readout conduction potential to one of said gates of said first and second memory cells and supplying a selection writing potential to the other gate at the time of data writing operation; a first surface channel layer provided in contact with said one surface in said channel region of said first memory cell, the conductivity type thereof being inverted only when said drain is grounded and one of the writing conduction potential and the selection writing potential is supplied; a first buried channel layer provided in contact with said first surface channel layer in said channel region of said first memory cell and having a carrier concentration lower than that of said first surface channel layer; a second surface channel layer provided in contact with said one surface in said channel region of said second memory cell, the conductivity type thereof being inverted only when said drain is grounded and one of the writing conduction potential and the selection writing potential is supplied; and a second buried channel layer provided in contact with said second surface channel layer in said channel region of said second memory cell and having a carrier concentration lower than that of said second surface channel layer. - View Dependent Claims (16, 17)
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18. A non-volatile semiconductor memory device comprising:
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a semiconductor substrate; and a memory cell with respect to which at least the data writing operation can be effected and which includes a channel region of a two-layered structure having a surface channel layer and a buried channel layer provided in said semiconductor substrate, a gate insulation film provided on said surface channel layer, a gate provided on said gate insulation film, and a charge storage layer provided in said gate insulation film; wherein the operation of reading out data from said memory cell is effected by using only said buried channel layer and determining data of "1" level or "0" level according to whether the conductivity type of said buried channel layer is the same as the conductivity type of said substrate or not; and
the operation of writing "0" level data into said memory cell is effected by using both of said surface channel layer and said buried channel layer, simultaneously making the conductivity types of said surface channel layer and said buried channel layer different from the conductivity type of said substrate, and passing a current into said surface channel layer and said buried channel layer to inject carriers into said charge storage layer. - View Dependent Claims (19, 20)
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21. A non-volatile semiconductor memory device comprising:
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a semiconductor substrate of one conductivity type; a memory cell including a channel region having a deep layer and a surface layer arranged between said deep layer and a surface of said semiconductor substrate, a control gate, and a charge storage layer; and a gate potential supplying circuit for supplying first and second potentials to said control gate, said first potential providing an inverted or non-inverted layer in said deep layer of said channel region based on data stored in said memory cell and said second potential causing the conductivity type of both said deep layer of said channel region and said surface layer of said channel region to be different than the one conductivity type of said semiconductor substrate. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A non-volatile semiconductor memory device, comprising:
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a body of semiconductor material of a first conductivity type; a non-volatile memory cell transistor having source and drain regions of a second conductivity type formed in said semiconductor body and defining a channel region therebetween, a control gate, and a charge storage layer, wherein said channel region includes a buried channel layer, and a surface channel layer formed between said buried channel layer and a surface of said semiconductor body; a gate potential supplying circuit for supplying a reading potential to said control gate during a data reading operation for reading data from said non-volatile memory cell transistor and for supplying a writing potential to said control gate during a data writing operation for writing data to said non-volatile memory cell transistor, wherein the conductivity type of said buried channel layer, but not said surface channel layer, is inverted or not inverted during the data reading operation based on the data read from said non-volatile memory cell transistor and the reading potential supplied to said control gate, and the conductivity type of both said buried channel layer and said surface channel layer is different than the conductivity type of said semiconductor body during the data writing operation based on the writing potential supplied to said control gate. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
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44. A semiconductor device, comprising:
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a body of semiconductor material of a first conductivity type; a transistor including source and drain regions of a second conductivity type formed in said semiconductor body and defining a channel region therebetween and a gate insulatively spaced from said channel region, wherein said channel region comprises at least two channel layers; and a gate potential supplying circuit for supplying a gate potential to said gate, wherein the conductivity types of said at least two channel layers are separately invertible in accordance with the gate potential supplied to said gate, and wherein said at least two channel layers comprise a buried channel layer, and a surface channel layer formed between said buried channel layer and a surface of said semiconductor body and the conductivity type of said buried channel layer, but not said surface channel layer, is inverted when the gate potential supplied to said gate turns said transistor ON.
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45. A non-volatile semiconductor memory device, comprising:
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a body of semiconductor material of a first conductivity type; a NAND memory cell block comprising a plurality of non-volatile memory cell transistors, each non-volatile memory cell transistor having source and drain regions of a second conductivity type formed in said semiconductor body and defining a channel region therebetween, a control gate, and a charge storage layer, wherein said channel region includes a buried channel layer, and a surface channel layer formed between said buried channel layer and a surface of said semiconductor body; a gate potential supplying circuit for supplying a reading potential to the gate of a first of said non-volatile memory cell transistors during a data reading operation for reading data from said first non-volatile memory cell transistor and for supplying a writing potential to the gate of a second of said non-volatile memory cell transistors during a data writing operation for writing data to said second non-volatile memory cell transistor, wherein the conductivity type of the buried channel layer, but not the surface channel layer, of said first non-volatile memory cell transistor is inverted or not inverted during the data reading operation based on the data read from said first non-volatile memory cell transistor and the reading potential supplied to the control gate of said first non-volatile memory cell transistor, and the conductivity type of both the buried channel layer and the surface channel layer of said second non-volatile memory cell transistor is different than the conductivity type of said semiconductor body during the data writing operation based on the writing potential supplied to the control gate of said second non-volatile memory cell transistor. - View Dependent Claims (46)
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47. A non-volatile semiconductor memory device, comprising:
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a body of semiconductor material of a first conductivity type; a memory cell having source and drain regions of a second conductivity type formed in said semiconductor body and defining a channel region therebetween, a control gate, and a charge storage layer, wherein said channel region includes a buried channel layer, and a surface channel layer of the first conductivity type formed between said buried channel layer and a surface of said semiconductor body; and a gate potential supplying circuit for supplying a reading potential to said control gate during a data reading operation for reading data from said memory cell and for supplying a writing potential to said control gate during a data writing operation for writing data to said memory cell, wherein, during the data reading operation, no current flows in said surface channel layer and the data is read from said memory cell based on a current flow or no current flow in said buried channel layer and, during the data writing operation, data is written to said memory cell based on a current flow in both said buried channel layer and said surface channel layer.
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48. A method of operating a non-volatile semiconductor memory device which includes a semiconductor substrate of one conductivity type;
- a memory cell with respect to which at least the data writing operation can be effected and which includes a threshold variable type transistor including a channel region having one surface and provided in said semiconductor substrate, a gate insulation film provided on said one surface of said channel region, a gate provided on said gate insulation film, and a charge storage layer provided in said gate insulation film;
a surface channel layer provided in contact with said one surface in said channel region; and
a buried channel layer provided in contact with said surface channel layer in said channel region, the method comprising the steps of;supplying a readout potential to said gate at the time of data readout operation to invert or not invert the conductivity type of said buried channel layer based on the readout data; and supplying a writing potential higher than the readout potential to said gate at the time of data writing operation to cause the conductivity type of both said buried channel layer and said surface channel layer to be different than the conductivity type of said semiconductor substrate. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61)
- a memory cell with respect to which at least the data writing operation can be effected and which includes a threshold variable type transistor including a channel region having one surface and provided in said semiconductor substrate, a gate insulation film provided on said one surface of said channel region, a gate provided on said gate insulation film, and a charge storage layer provided in said gate insulation film;
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62. A method of operating a non-volatile semiconductor memory device which includes a semiconductor substrate of a first conductivity type;
- a first memory cell with respect to which at least the data writing operation can be effected and which includes a threshold variable type transistor including a channel region having one surface and provided in said semiconductor substrate, a gate insulation film provided on said one surface of said channel region, a gate provided on said gate insulation film, a charge storage layer provided in said gate insulation film, a first terminal region of a second conductivity type provided in contact with said channel region in said substrate, and a second terminal region of said second conductivity type connected to a source and provided in contact with said channel region in said substrate;
a first surface channel layer provided in contact with said one surface in said channel region of said first memory cell;
a first buried channel layer provided in contact with said first surface channel layer in said channel region of said first memory cell and having a carrier concentration lower than that of said first surface channel layer;
a second memory cell with respect to which at least the data writing operation can be effected and which includes a threshold variable type transistor including a channel region having one surface and provided to said semiconductor substrate, a gate insulation film provided on said one surface of said channel region, a gate provided on said gate insulation film, a charge storage layer provided in said gate insulation film, a first terminal region of said second conductivity type provided in contact with said channel region in said substrate and connected to said first terminal region of said first memory cell, and a second terminal region of said second conductivity type connected to a drain and provided in contact with said channel region in said substrate;
a second surface channel layer provided to contact with said one surface in said channel region of said second memory cell; and
a second buried channel layer provided in contact with said second surface channel layer in said channel region of said second memory cell and having a carrier concentration lower than that of said second surface channel layer, the method comprising the steps of;supplying readout conduction potential to one of said gates of said first and second memory cells and supplying a selection readout potential to the other gate at the time of data readout operation; and supplying a writing conduction potential higher than the readout conduction potential to one of said gates of said first and second memory cells and supplying a selection writing potential to the other gate at the time of data writing operation to invert the conductivity type of one of said first and second surface channel layers. - View Dependent Claims (63, 64)
- a first memory cell with respect to which at least the data writing operation can be effected and which includes a threshold variable type transistor including a channel region having one surface and provided in said semiconductor substrate, a gate insulation film provided on said one surface of said channel region, a gate provided on said gate insulation film, a charge storage layer provided in said gate insulation film, a first terminal region of a second conductivity type provided in contact with said channel region in said substrate, and a second terminal region of said second conductivity type connected to a source and provided in contact with said channel region in said substrate;
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65. A method of operating a non-volatile semiconductor memory device which includes a semiconductor substrate of one conductivity type;
- and a memory cell including a channel region having a deep layer and a surface layer arranged between said deep layer and a surface of said semiconductor substrate, a control gate, and a charge storage layer, the method comprising the steps of;
supplying a first potential to said control gate, said first potential providing an inverted or non-inverted layer in said deep layer of said channel region based on the data stored in said memory cell; and supplying a second potential to said control gate, said second potential causing the conductivity type of both said channel region and said surface layer of said channel region to be different than the conductivity type of said semiconductor substrate. - View Dependent Claims (66, 67, 68, 69, 70, 71, 72, 73, 74)
- and a memory cell including a channel region having a deep layer and a surface layer arranged between said deep layer and a surface of said semiconductor substrate, a control gate, and a charge storage layer, the method comprising the steps of;
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75. A method of operating non-volatile semiconductor memory device which includes a body of semiconductor material of a first conductivity type;
- and a non-volatile memory cell transistor having source and drain regions of a second conductivity type formed in said semiconductor body and defining a channel region therebetween, a control gate, and a charge storage layer, wherein said channel region includes a buried channel layer, and a surface channel layer formed between said buried channel layer and a surface of said semiconductor body, the method comprising the steps of;
supplying a reading potential to said control gate during a data reading operation for reading data from said non-volatile memory cell transistor; and supplying a writing potential higher than the reading potential to said control gate during a data writing operation for writing data to said non-volatile memory cell transistor, wherein the conductivity type of said buried channel layer, but not said surface channel layer, is inverted or not inverted during the data reading operation based on the data read from said non-volatile memory cell transistor and the reading potential supplied to said control gate, and the conductivity type of both said buried channel layer and said surface channel layer is different than the conductivity type of said semiconductor body during the data writing operation based on the writing potential supplied to said control gate. - View Dependent Claims (76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87)
- and a non-volatile memory cell transistor having source and drain regions of a second conductivity type formed in said semiconductor body and defining a channel region therebetween, a control gate, and a charge storage layer, wherein said channel region includes a buried channel layer, and a surface channel layer formed between said buried channel layer and a surface of said semiconductor body, the method comprising the steps of;
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88. A method of operating a non-volatile semiconductor memory device which includes a body of semiconductor material of a first conductivity type;
- a NAND memory cell block comprising a plurality of non-volatile memory cell transistors, each non-volatile memory cell transistor having source and drain regions of a second conductivity type formed in said semiconductor body and defining a channel region therebetween, a control gate, and a charge storage layer, wherein said channel region includes a buried channel layer, and a surface channel layer formed between said buried channel layer and a surface of said semiconductor body, the method comprising the steps of;
supplying a reading potential to the gate of a first of said non-volatile memory cell transistors during a data reading operation for reading data from said first non-volatile memory cell transistor; and supplying a writing potential higher than the reading potential to the gate of a second of said non-volatile memory cell transistors during a data writing operation for writing data to said second non-volatile memory cell transistor, wherein the conductivity type of the buried channel layer, but not the surface channel layer, of said first non-volatile memory cell transistor is inverted or not inverted during the data reading operation based on the data read from said first non-volatile memory cell transistor and the reading potential supplied to the control gate of said first non-volatile memory cell transistor, and the conductivity type of both the buried channel layer and the surface channel layer of said second non-volatile memory cell transistor is different than the conductivity type of said semiconductor body during the data writing operation based on the writing potential supplied to the control gate of said second non-volatile memory cell transistor. - View Dependent Claims (89)
- a NAND memory cell block comprising a plurality of non-volatile memory cell transistors, each non-volatile memory cell transistor having source and drain regions of a second conductivity type formed in said semiconductor body and defining a channel region therebetween, a control gate, and a charge storage layer, wherein said channel region includes a buried channel layer, and a surface channel layer formed between said buried channel layer and a surface of said semiconductor body, the method comprising the steps of;
Specification