Strongly fail-safe interface based on concurrent checking

• US 5,586,124 A
• Filed: 05/01/1995
• Issued: 12/17/1996
• Est. Priority Date: 09/02/1993
• Status: Expired due to Term

• Current Assignee: IROC Technologies Incorporated
• Original Assignee: Sofia Koloni, Ltd.
• Inventors: Nicolaidis, Michael
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/428,228
• Time in Patent Office: 596 Days
• Field of Search: 371/25.1, 371/27, 371/22.6, 371/72, 371/68.1
• US Class Current: 714/736
• CPC Class Codes: G06F 11/0796 Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
• CPC Class Codes: G06F 11/085 using codes with inherent redundancy, e.g. n-out-of-m codes
• CPC Class Codes: H03K 19/0075 by using two redundant chains

Abstract

The present invention relates to a fail-safe control interface including branches for providing signals having a safe state or a non-safe state. Each branch comprises inputs for receiving at least two binary control signals (Si, Si*); a source of a non-safe state (Fe) connectable through a basic chain of elements (14, 15) to an output (Oi) when the control signals realize a predetermined combination; a concurrent checker (17) providing an error detection signal (g1, g2) if the inputs of a pair of its inputs are at predetermined states; and means (14*) for providing a first input of said pair of inputs with a signal corresponding to the state of said output and the second input of said pair of inputs with a signal corresponding to the output of a duplicate chain of the basic chain, this duplicate chain reacting like the basic chain in response to the control signals.

Claims

1. Fail-safe circuit branch for providing a signal having a safe state or a non-safe state, comprising:

inputs for receiving at least two binary control signals (Si, Si*);

a source of a non-safe state (Fe) connectable through a basic chain (14,

     15) to an output (Oi) when the control signals realize a predetermined combination;

a concurrent checker (17) providing an error detection signal (g1, g2) if the inputs of a pair of its inputs are at predetermined states; and

means (14, 14*) for providing a first input of said pair of inputs with a signal corresponding to the state of said output and the second input of said pair of inputs with a signal corresponding to the output of a duplicate chain of the basic chain, this duplicate chain reacting like the basic chain in response to the control signals.

2. A fail-safe circuit comprising:

a plurality of fail-safe branches according to claim 1, all sharing a common concurrent checker; and

a non-fail-safe combining circuit receiving the outputs of the branches, this combining circuit being such that it lacks a source of the non-safe state and that it provides a non-safe state output if one or more branches provide the non-safe state.

3. A fail-safe logic circuit according to claim 2, wherein the combining circuit realizes an OR function, comprising:

a plurality of logic inputs corresponding to the binary control signals of the branches; and

for each combination of the logic inputs that should generate an non-safe state of the logic circuit, a branch that transfers the non-safe state to the combining circuit when the logic inputs realize this combination.

4. A two-input exclusive OR circuit according to claim 3, comprising two branches, one transferring the non-safe state for the combination 1, 0 of the inputs, and the other for the combination 0, 1.

5. A fail-safe control interface according to claim 1, comprising, in the basic chain, at least one switch (14) controlled by one of the binary control signals (Si) and means for irreversibly cutting the power of the interface if the concurrent checker provides an error detection signal.

6. A fail-safe control interface according to claim 5, wherein the concurrent checker is a double-rail checker (17) having two outputs (g1, g2) providing the error detection signal (Oe) through an exclusive OR circuit (37) the branches of the exclusive OR circuit and the branch of the interface sharing the double-rail checker.

7. A fail-safe control interface according to claim 6, comprising, between the exclusive OR circuit (37) and the double-rail checker (17), an error indicator lock circuit (36).

8. A fail-safe control interface according to claim 7, comprising two exclusive OR circuits (37, 38) both provided with the outputs of the error indicator lock (36) and sharing the double-rail checker, the branches of a first of the exclusive OR circuits being connected to the non-safe state (Fe), and the branches of the second being connected to the output of the first.

9. A fail-safe control interface according to claim 2 realising a majority voter, comprising:

three branches each receiving a different pair of control signals (S¹, S², S³); and

a non-fail-safe combining block that transfers the non-safe state to its output whenever this state is present at the output of at least one branch.