High speed segmented neural network and fabrication method
First Claim
1. A method for emulating a feed forward, segmented neural network having a large number of inputs, said method comprising the steps of:
- (a) modeling a segmented neural network having a large number of inputs as multiple network layers of subnetworks segmented such that each subnetwork within a network layer receives totally different inputs than all other subnetworks within said network layer, a plurality of said multiple network layers each having an even number of segmented subnetworks, each subnetwork comprising a plurality of interconnected sublayers, each sublayer having a plurality of processing nodes, and each subnetwork being sized for realization as a single binary memory device;
(b) training the segmented neural network modeled in step (a) while requiring that input and output values of each network layer comprise binary signals;
(c) mapping all possible input and corresponding output values of each subnetwork of said trained segmented neural network;
(d) storing the mapped input and output values of each subnetwork in an associated binary memory device such that behavior of each subnetwork of the trained segmented neural network is emulated completely by the associated binary memory device; and
(e) electrically interconnecting associated binary memory devices in a circuit arrangement corresponding to connection of the subnetworks in the modeled segmented neural network.
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Abstract
A high speed, feed forward, segmented neural network and fabrication technique are described. The segmented network includes a plurality of network layers stacked in an ascending pyramid fashion. The network layers are structured with a plurality of subnetworks, and within each subnetwork exists a plurality of nodes structured in a fully interconnected and/or partially interconnected layered neural network arrangement. The inputs and outputs of each subnetwork are one bit digital values constrained to `0` or `1`, while any number of nodes with any number of layers may be modeled for each subnetwork. Each subnetwork is independent of all other subnetworks in a given network layer, and thus, each network layer is segmented. In hardware implementation, each subnetwork comprises a simple memory device, such as a RAM or PROM look-up table. The speed of the neural network system is high and largely dictated by the access time of the memory devices used.
30 Citations
9 Claims
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1. A method for emulating a feed forward, segmented neural network having a large number of inputs, said method comprising the steps of:
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(a) modeling a segmented neural network having a large number of inputs as multiple network layers of subnetworks segmented such that each subnetwork within a network layer receives totally different inputs than all other subnetworks within said network layer, a plurality of said multiple network layers each having an even number of segmented subnetworks, each subnetwork comprising a plurality of interconnected sublayers, each sublayer having a plurality of processing nodes, and each subnetwork being sized for realization as a single binary memory device; (b) training the segmented neural network modeled in step (a) while requiring that input and output values of each network layer comprise binary signals; (c) mapping all possible input and corresponding output values of each subnetwork of said trained segmented neural network; (d) storing the mapped input and output values of each subnetwork in an associated binary memory device such that behavior of each subnetwork of the trained segmented neural network is emulated completely by the associated binary memory device; and (e) electrically interconnecting associated binary memory devices in a circuit arrangement corresponding to connection of the subnetworks in the modeled segmented neural network. - View Dependent Claims (2, 3)
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4. A method for emulating a feed forward, segmented neural network having a large number of inputs, said method comprising the steps of:
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(a) modeling a segmented neural network having a large number of inputs as multiple network layers of subnetworks segmented such that each subnetwork within a network layer receives totally different inputs than all other subnetworks within said network layer, each subnetwork comprising a plurality of interconnected sublayers, each sublayer having a plurality of processing nodes, and each subnetwork being sized for realization as a single binary memory device, said modeling step including modeling the segmented neural network to have a plurality of network layers each having an even number of segmented subnetworks, said modeling step further comprising modeling the segmented neural network such that the total number of inputs, the total number of subnetworks, and the total number of outputs of each network layer is one half of the total number of inputs, the total number of subnetworks and the total number of outputs, respectively, of an immediately preceding network layer; (b) training the segmented neural network modeled in step (a) while requiring that input and output values of each network layer comprise binary signal; (c) mapping all possible input and corresponding output values of each subnetwork of said trained segmented neural network; (d) storing the mapped input and output values of each subnetwork in an associated binary memory device such that behavior of each subnetwork of the trained segmented neural network is emulated completely by the associated binary memory device; and (e) electrically interconnecting associated binary memory devices in a circuit arrangement corresponding to connection of the subnetworks in the modeled segmented neural network.
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5. Apparatus for emulating a trained feed forward, segmented neural network having a large number of inputs and multiple network layers of subnetworks, each layer comprising at least one subnetwork, each subnetwork comprising a plurality of processing nodes in an interconnected sublayered arrangement, each subnetwork of each network layer receiving totally different inputs than all other subnetworks of said layer, and each subnetwork being sized for realization as a single binary memory device, said multiple network layers being arranged in pyramidal fashion from an input network layer to an output network layer such that the number of subnetworks in said multiple network layers decreases from said input network layer to said output network layer, said apparatus comprising:
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a plurality of binary memory devices equal in number to the number of said subnetworks of the trained segmented neural network, each binary memory device being associated with a respective subnetwork and storing a complete set of mapped input and output values of the subnetwork such that behavior of the subnetwork within the trained segmented neural network is completely emulated by the associated binary memory device, wherein each of said binary memory devices has M inputs and N outputs, wherein N=M/2, and M and N are integers greater than 0; and means for electrically interconnecting the plurality of binary memory devices in a circuit arrangement which corresponds to said segmented neural network. - View Dependent Claims (6, 7, 8, 9)
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Specification