Devices and systems with parallel logic unit operable on data memory locations, and methods

• US 5,586,275 A
• Filed: 04/26/1994
• Issued: 12/17/1996
• Est. Priority Date: 05/04/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Boutaud, Frederic, Ehlig, Peter N.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/233,477
• Time in Patent Office: 966 Days
• Field of Search: 364/424.01, 364/424.05, 395/375, 395/800, 395/500
• US Class Current: 712/223
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/3652 in-circuit-emulation [ICE] arrangements
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

A data processing device includes a data bus and a program bus, a data memory connected to the data bus and having data memory locations, and an electronic computation unit connected to the data bus and an accumulator connected to the electronic computation unit and to the data bus. A logic circuit is connected to the program bus for receiving instructions and connected to the data bus for executing logic operations in accordance with at least some of the instructions. The logic operations affect bits in at least one of the data memory locations independently of the electronic computation unit without affecting the accumulator. A control circuit sends instructions to the logic circuit on the program bus and to the electronic computation unit. Other devices, systems and methods are also disclosed.

Claims

1. A data processing device, comprising:

a data bus;

a program bus;

a data memory connected to said data bus and having data memory locations;

an electronic computation unit connected to said data bus and to said program bus;

an accumulator connected to said electronic computation unit and to said data bus;

logic circuit connected to said program bus for receiving instructions and connected to said data bus for executing logic operations in accordance with at least some of the instructions, the logic operations affecting bits in at least one of said data memory locations independently of said electronic computation unit and without affecting said accumulator; and

control circuit for sending instructions to said logic circuit on said program bus and to said electronic computation unit.

2. The data processing device of claim 1 wherein the logic operations include an operation of writing a bit pattern comprising a full data word into a selected data memory location of said data memory.

3. The data processing device of claim 1 wherein the logic operations include an operation of setting particular bits to one in a data word at a selected data memory location without affecting other bits in said data word.

4. The data processing device of claim 1 wherein the logic operations include an operation of clearing particular bits in a data word at a selected data memory location without affecting other bits in said data word.

5. The data processing device of claim 1 wherein the logic operations include an operation of toggling particular bits in a data word at a selected data memory location without affecting the other bits in said data word.

6. The data processing device of claim 1 wherein said logic circuit includes circuitry for comparing a first word having a plurality of bits against a data word at a selected data memory location without modifying the data word and producing a bit indicative of a result of the comparison.

7. The data processing device of claim 1 wherein said logic circuit includes circuitry for testing a particular bit in a data word at a selected data memory location without modifying the data word and effecting a branch operation of said control circuit depending on a result of the testing.

8. The data processing device of claim 1 wherein said logic circuit includes logic circuitry having a first input connected for receiving data from said data bus, an output for sending data to said data bus, and a second input selectively operable to receive a word either from said data bus or said program bus.

9. The data processing device of claim 1 wherein said logic circuit includes logic circuitry having first and second inputs, the first input connected for receiving data from said data bus, a register connected to said data bus;

and a multiplexer selectively operable to connect either said program bus or said register to said second input of said logic circuitry, said logic circuitry further having an output for sending data to said data bus.

10. The data processing device of claim 1 wherein said logic circuit includes logic circuitry and a register each having an input connected to said data bus, said logic circuitry having a further input for receiving data from said register and an output for sending data to said data bus as a result of executing one of said logic operations.

11. The data processing device of claim 10 wherein said control circuit includes circuitry for storing the contents of said accumulator to said register and said logic circuit includes circuitry for sending to said data bus the contents of said register modified by a logical operation.

12. The data processing device of claim 10 wherein said logic circuit includes circuitry for sending to said data bus the contents of said register with selected bits toggled.

13. The data processing device of claim 10 wherein said logic circuit includes circuitry for sending to said data bus the contents of said register with selected bits set to one.

14. The data processing device of claim 10 wherein said logic circuit includes circuitry for sending to said data bus the contents of said register with selected bits cleared.

15. The data processing device of claim 1 further comprising a semiconductor chip wherein said data bus, program bus, data memory, electronic computation unit, logic circuit and control circuit are all provided on said semiconductor chip.

16. The data processing device of claim 1 wherein said data memory comprises a first integrated circuit and said electronic computation unit, logic circuit and control circuit together comprise a second integrated circuit, and said first and second integrated circuits are interconnected.

17. A method of operating a data processing device having a data memory, an arithmetic logic unit and an accumulator, comprising the steps of

generating instructions for operating said arithmetic logic unit and accumulator;

and

generating additional instructions and executing logic operations in accordance with at least some of the additional instructions to set, clear, and toggle particular bits of selected data words in said data memory independently of said arithmetic logic unit and without affecting said accumulator.