Method and apparatus for the reduction of tablewalk latencies in a translation look aside buffer

• US 5,586,283 A
• Filed: 10/07/1993
• Issued: 12/17/1996
• Est. Priority Date: 10/07/1993
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Lopez-Aguado, Herbert, Mehring, Peter A.
• Primary Examiner(s): Lane, Jack A.
• Application Number:
  US08/132,796
• Time in Patent Office: 1,167 Days
• Field of Search: 395/400, 395/416, 395/417
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/684 TLB miss handling

Abstract

A translation look aside buffer including virtual page table pointer tags provides a system and method for accessing page table entries in page memory of the translation look aside buffer with decrease latencies caused by accesses to increasing levels of page tables during a table walk of the page table. Virtual tags identifying page table pointers at a predetermined level of the page table higher than the initial context level of the page table are included in the tag memory of the translation look aside buffer. These virtual tags provide a pointer which directly points to the page table pointer at that predetermined level of the page table. Therefore, if a TLB miss occurs wherein a tag for a page table entry corresponding to the virtual address is not found, a comparison is performed to determined if a corresponding virtual tag PTP is located in the tag memory. If the corresponding virtual tag PTP is found in the tag memory, access is gained to the PTP in the page table without the need for performing a time consuming table walk through the lower levels of the page table.

Claims

1. In a computer system comprising a processor and memory, wherein accesses to memory are performed by issuing a virtual address to memory, an apparatus for performing a translation from a virtual address to a physical address comprising:

a translation look aside buffer comprising;

a page table memory comprising a plurality of levels of a page table, an initial level of the page table being identified as a root level, said page table memory storing page table pointers (PTPs) which provide a base address of a table in a next higher level of a page table and page table entries (PTEs) which provide information to translate the virtual address to the physical address;

a tag memory comprising tags, said tags comprising identification of PTEs and PTPs, said tags further comprising virtual PTP tags for PTPs located in at least one predetermined higher level that is higher than the root level, said tags providing a pointer to a corresponding entry in the page table;

a select mechanism coupled to receive the virtual address and context of the memory access, said select mechanism generating a compare virtual PTP tag if a TLB miss occurs when trying to access a tag identifying a PTE corresponding to the virtual address, said compare virtual PTP tag generated from the context of the memory address and a predetermined portion of the virtual address, said compare virtual PTP tag compared to stored virtual PTP tags stored in the tag memory such that if the compared virtual PTP tag and one of the stored virtual PTP tags match, the select mechanism provides a pointer to the corresponding PTP at the predetermined higher level of the page table without performing a page table walk initiating at the root level through the lower level page tables;

wherein the time expended for performing a page table walk is minimized.

2. The computer system as set forth in claim 1, wherein virtual PTP tags identify PTPs in one higher level.

3. The computer system as set forth in claim 2, wherein virtual PTP tags identify PTPs in a lower level next to the highest level of the page table.

4. The computer system as set forth in claim 1, wherein the page table comprises a root, first, second and third levels, PTEs are stored at least in the third level of the page table, and PTPs are stored in the root, first, second and third levels of the page table, said predetermined higher level being the second level of the page table, such that if a match of any one of the stored virtual PTP tags and compare virtual PTP tags occurs, a table walk through the root, first and second levels to identify the PTP in the second level is avoided.

5. The computer system as set forth in claim 1, wherein the virtual address comprises a plurality of index fields, each index field providing an index to an entry in a corresponding level of the page table, said virtual PTP tag generated from the context and index fields corresponding to the lower levels of the page tables and the predetermined higher level of the page table.

6. The computer system as set forth in claim 5, wherein the virtual PTP tag for a PTP in the second level is generated from the context and a first and second index field corresponding respectively to the first and second levels of the page table.

7. In a computer system comprising a processor and memory, wherein accesses to memory are performed by issuing a virtual address to memory, an apparatus for performing a translation from a virtual address to a physical address comprising:

a memory management unit (MMU) comprising a data path for receiving a context of a memory access and a virtual address and outputting a physical address to access memory and a controller for controlling translation of virtual addresses to physical addresses;

a translation look aside buffer comprising;

a page table memory comprising a plurality of levels of a page table, an initial level of the page table being identified as a root level, said page table memory storing page table pointers (PTPs) which provide a base address of a table in a next higher level of a page table and page table entries (PTEs) which provide information to translate the virtual address to the physical address; and

a tag memory comprising tags identifying PTEs and PTPs, said tags identifying a table comprising virtual PTP tags for PTPs located in at least one predetermined higher level that is higher than the root level, said tags providing a pointer to a corresponding entry in the page table;

said MMU controller generating a compare virtual PTP tag if a TLB miss occurs when to access a tag identifying a PTE corresponding to the virtual address, said compare virtual PTP tag generated from the context of the memory address and a predetermined portion of the virtual address and the content of the memory address where the miss occurred, said compare virtual PTP tag compared to stored virtual PTP tags stored in the tag memory such that if the compared virtual PTP tag and one of the stored virtual PTP tags match, said controller providing a pointer to the corresponding PTP at the predetermined higher level of the page table without performing a page table walk initiating at the root level through the lower level page tables;

wherein the time expended for performing a page table walk is minimized.

8. The computer system as set forth in claim 7, wherein virtual PTP tags identify PTPs in one higher level.

9. The computer system as set forth in claim 8, wherein virtual PTP tags identify PTPs in a lower level next to the highest level of the page table.

10. The computer system as set forth in claim 7, wherein the page table comprises a root, first, second and third levels, PTEs are stored at least in the third level of the page table, and PTPs are stored in the root, first, second and third levels of the page table, said predetermined higher level being the second level of the page table, such that if a match of any one of the stored virtual PTP tags and compared virtual PTP tags occurs, a table walk through the root, first and second levels to identify the PTP in the second level is avoided.

11. The computer system as set forth in claim 7, wherein the virtual address comprises a plurality of index fields, each index field providing an index to an entry in a corresponding level of the page table, said virtual PTP tag generated from the context and index fields corresponding to the lower levels of the page tables and the predetermined higher level of the page table.

12. The computer system as set forth in claim 11, wherein the virtual PTP tag for a PTP in the second level is generated from the context and a first second index field corresponding respectively to the first and second levels of the page table.

13. In a computer system comprising a processor and memory, wherein accesses to memory are performed by issuing a virtual address to memory, said system further comprising a translation look aside buffer comprising a tag memory and a page table memory, said page table memory comprising a plurality of levels of a page table, an initial level of the page table being identified as a root level, said page table memory storing page table pointers (PTPs) which provide a base address of a table in a next higher level of a page table and page table entries (PTEs) which provide information to translate the virtual address to the physical address, said tag memory comprising tags identifying PTEs and PTPs, a method for performing a translation from a virtual address to a physical address comprising the steps of:

storing virtual PTP tags for PTPs located in at least one predetermined higher level higher than the root level, said tags providing a pointer to a corresponding entry in the page table; and

if a TLB miss occurs when trying to access a tag identifying a PTE corresponding to the virtual address;

generating a compare virtual PTP tag, said compare virtual PTP tag generated from the context of the memory address and a predetermined portion of the virtual address and the content of the memory address where the miss occurred,

comparing said compare virtual PTP tag to the stored virtual PTP tags stored in the tag memory, and

if the compared virtual PTP tag and one of the stored virtual PTP tags match, providing a pointer to the corresponding PTP at the predetermined higher level of the page table without performing a page table walk initiated at the root level through the lower level page tables;

wherein the time expended for performing a page table walk is minimized.

14. The method as set forth in claim 13, wherein virtual PTP tags identify PTPs in one higher level.

15. The method as set forth in claim 14, wherein virtual PTP tags identify PTPs in a lower level next to the highest level of the page table.

16. The method as set forth in claim 13, wherein the page table comprises a root, first, second and third levels, PTEs are stored at least in the third level of the page table, and PTPs are stored in the root, first, second and third levels of the page table, said predetermined higher level being the second level of the page table, such that if a match of any one of the stored virtual PTP tags and compared virtual PTP tags occurs, a table walk through the root, first and second levels to identify the PTP in the second level is avoided.

17. The method as set forth in claim 13, wherein the virtual address comprises a plurality of index fields, each index field providing an index to an entry in a corresponding level of the page table, said step of generating a virtual PTP tag comprising the step of generating the tag from the context and index fields corresponding to the lower levels of the page tables and the predetermined level of the page table.

18. The computer system as set forth in claim 17, wherein the virtual PTP tag for a PTP in the second level is generated from the context and a first and second index field corresponding respectively to the first and second levels of the page table.