Process for manufacturing a stacked integrated circuit package

• US 5,587,341 A
• Filed: 10/18/1994
• Issued: 12/24/1996
• Est. Priority Date: 06/24/1987
• Status: Expired due to Term

• Current Assignee: Akita Electronics Company Limited, Hitachi, Ltd., Hitachi TOBU Semiconductor Limited (Hitachi, Ltd.)
• Original Assignee: Akita Electronics Company Limited, Hitachi, Ltd., Hitachi TOBU Semiconductor Limited (Hitachi, Ltd.)
• Inventors: Toshio, Sugano, Masayuki, Watanabe, Yoshiaki, Wakashima, Seiichiro, Tsukui, Takashi, Ono
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US08/323,709
• Time in Patent Office: 798 Days
• Field of Search: 257/723, 257/724, 257/725, 257/666.3, 257/666.4, 257/686, 257/777, 361/735, 361/813, 439/69, 437/208, 437/915, 437/206
• US Class Current: 438/109
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/1005 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2225/1029 : the support being a lead frame
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/49572 : consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/50 : Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 : using tape automated bonding [TAB]
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/10681 : Tape Carrier Package [TCP]; Flexible sheet connector
• CPC Class Codes: H05K 2203/1572 : Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 3/3447 : Lead-in-hole components H05K3/3415 takes precedence
• CPC Class Codes: H05K 3/368 : parallel to each other H05K3/361 takes precedence

Abstract

In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Claims

1. A method of fabricating a semiconductor memory module comprising the steps of:

providing first and second semiconductor memory chips having respective first and second sets of terminals, each set of terminals including at least one chip-select terminal and a plurality of non-chip-select terminals;

providing first and second plastic film tapes having respective first and second device holes sized to accommodate respective said first and second memory chips;

forming a first set of leads on said first film tape, said first set of leads protruding into said first device hole and comprising a first plurality of non-chip-select leads having a first pattern and a first chip-select lead having a first arrangement;

forming a second set of leads on said second film tape, said second set of leads protruding into said second device hole and comprising a second plurality of non-chip-select leads having a second pattern substantially identical to said first pattern and a second chip-select lead having a second arrangement different from said first arrangement;

bonding said first and second sets of leads to respective said first and second sets of terminals;

stacking said first chip bonded to said first set of leads on top of said second chip bonded to said second set of leads with said first pattern superimposed on said second pattern and said first arrangement not superimposed on said second arrangement;

bonding each lead in said first plurality of non-chip-select leads to a corresponding lead in said second plurality of leads, said corresponding lead being the lead on which said each lead is superimposed.

providing a base plate having a first and a second face; and

mounting said stacked first and second chips onto said base plate'"'"'s first face.

2. The method of claim 1 wherein said film tape is a polyimide resin film tape.

3. The method of claim 2 comprising the additional step of forming bump electrodes on said terminals before bonding said leads to said terminals.

4. The method of claim 2 wherein thermocompression bonding is used to bond said first plurality of non-chip-select leads to said second plurality of non-chip-select leads.

5. The method of claim 1 comprising the additional step of mounting a stacked third and fourth chip onto said base plate'"'"'s second face, said stacked third and fourth chips being substantially identical to said stacked first and second chips.

6. A method of fabricating a semiconductor memory module comprising the steps of:

providing a base plate having a first and a second face;

providing at least four semiconductor memory chips, each chip having at least one chip-select terminal and a plurality of corresponding non-chip-select terminals;

connecting a chip-select lead to said at least one chip-select terminal and corresponding leads to said plurality of corresponding terminals;

stacking a first chip on top of a second chip, said first and second chips oriented such that corresponding terminals on said first chips are aligned with corresponding terminals on said second chip;

stacking a third chip on top of a fourth chip, said third and fourth chips oriented such that corresponding terminals on said third chips are aligned with corresponding terminals on said fourth chip;

superimposing and connecting only said corresponding leads on said first chip with corresponding leads on said second chip;

superimposing and connecting only said corresponding leads on said third chip with corresponding leads on said fourth chip;

mounting said stacked first and second chips onto the face of said base plate; and

mounting said stacked third and fourth chips onto the second face of said base plate.

7. The method of claim 6 wherein a tape automated bonding process is used to connect the leads to the chip terminals on each chip, said tape automated bonding process including the step of forming said leads on a plastic film tape.

8. The method of claim 7 comprising the additional step of forming bump electrodes on the terminals of each chip prior to tape automated bonding said leads to said chip terminals.

9. The method of claim 8 wherein thermocompression bonding is used to connect said first chip'"'"'s corresponding leads to said second chip'"'"'s corresponding leads and to connect said third chip'"'"'s corresponding leads to said fourth chip'"'"'s corresponding leads.

10. The method of claim 6 wherein the first chip'"'"'s chip-select terminal is not aligned with the second chip'"'"'s chip-select terminal when said first and second chips are stacked and the third chip'"'"'s chip-select terminal is not aligned with the fourth chip'"'"'s chip-select terminal when said third and fourth chips are stacked.

11. A method of fabricating a semiconductor memory module comprising the steps of:

preparing a first semiconductor device and a second semiconductor device, said first device having a first rectangular shaped semiconductor chip, first leads and a second lead, said first chip including first external terminals and a second external terminal formed on a main surface thereof, one end of said first leads and said second lead being electrically connected with said first external terminals and said second external terminals respectively, said second device having a second rectangular shaped semiconductor chip, third leads and a fourth lead, said second rectangular shaped semiconductor chip including third external terminals and a fourth external terminal formed on a main surface thereof, one ends of said third leads and said fourth lead being electrically connected with said third external terminals and said fourth external terminal respectively, said first and second chips being substantially identical, said first and third external terminals being arranged at the same positions on said main surface, said second and fourth external terminals being arranged at the same positions on said main surface, said first and second leads extending in a downward direction in a substantially straight line from said first chip and said third and fourth leads extending in a downward direction in a substantially straight line from said second chip;

stacking said second device over said first device such that the other ends of said third leads of said second device are directly connected with said first leads, and said second lead of said first device and said fourth lead of said second device are electrically independent from each other;

preparing a printed circuit board having a main surface and a rear surface with first electrodes, a second electrode and a third electrode formed on said main surface, said second and third electrodes being electrically independent from each other; and

mounting said first and second devices on said primed circuit board such that the other ends of said first leads of said first device are electrically connected with said first electrodes of said printed circuit board, and the other end of said second lead of said first device and the other end of said fourth lead of said second device are directly connected with respective said second and third electrodes of said printed circuit board.

12. A method of fabricating a semiconductor memory module according to claim 11, wherein each of said second lead and said fourth lead is a chip-selecting signal lead, and wherein said second lead and said fourth lead are arranged in different positions in the plane view.

13. A method of fabricating a semiconductor memory module according to claim 12, wherein said first and third leads are common signal leads.

14. A method of fabricating a semiconductor memory module according to claim 11, wherein said first to fourth leads are electrically connected with said first to fourth external terminals by bump electrodes formed on said first to fourth external terminals.

15. A method of fabricating a semiconductor memory module according to claim 11, wherein said first and second external terminals are arranged along facing sides of said first chip, and wherein said third and fourth external terminals are arranged along facing sides of said chip.

16. A method of fabricating a semiconductor memory module according to claim 11, wherein said leads are connected to said terminals by a tape automated bonding process.

17. A method of fabricating a semiconductor memory module according to claim 11, further comprising the steps of:

preparing a third semiconductor device and a fourth semiconductor device, said third semiconductor device having a third rectangular shaped semiconductor chip, fifth leads and a sixth lead, said third chip including fifth external terminals and a sixth external terminal formed on a main surface thereof, one ends of said fifth leads and said sixth lead being electrically connected with said fifth external terminals and said sixth external terminals respectively, said fourth semiconductor device having a fourth rectangular shaped semiconductor chip, seventh leads and an eighth lead, said fourth chip including seventh external terminals and an eighth external terminal formed on a main surface thereof, one end of said seventh leads and said eighth lead being electrically connected with said seventh external terminals and said eight external terminals respectively, said third and fourth chips being substantially identical, said fifth and seventh external terminals being arranged at the same positions on said main surface, said sixth and eighth external terminals being arranged at the same positions on said main surface, said fifth and sixth leads extending in a downward direction in a substantially straight line from said third chip and said seventh and eighth leads extending in a downward direction in a substantially straight line from said fourth chip;

stacking said fourth device over said third device such that the other ends of said seventh leads of said fourth device are directly connected with said fifth leads, and said sixth lead of said third device and said eighth lead of said fourth device are electrically independent from each other; and

mounting said third and fourth devices on said printed circuit board such that the other ends of said fifth leads of said third device are electrically connected with fourth electrodes formed on the rear surface of said printed circuit board, and the other end of said sixth lead of said third device and the other end of said eighth lead of said fourth device are directly connected with respective fifth and sixth electrodes also formed on the rear surface of said printed circuit board.