Two-transistor zero-power electrically-alterable non-volatile latch

• US 5,587,603 A
• Filed: 01/06/1995
• Issued: 12/24/1996
• Est. Priority Date: 01/06/1995
• Status: Expired due to Term

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Kowshik, Vikram
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Abraham, Fetsum
• Application Number:
  US08/369,760
• Time in Patent Office: 718 Days
• Field of Search: 257/300, 257/303, 257/316, 257/318, 257/320, 257/337, 257/334, 257/315, 257/321
• US Class Current: 257/316
• CPC Class Codes: H03K 17/24 Storing the actual state when the supply voltage fails
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A two-transistor, zero-power, electrically-alterable non-volatile latch element comprises an input node, an output node, and an erase node. A P-Channel MOS transistor has a source connected to a source of first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate. An N-Channel MOS transistor has a source connected to a source of second electrical potential lower than the first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate and electrically connected to the floating gate of the P-Channel MOS transistor. The floating gates of the P-Channel MOS transistor and the N-Channel MOS transistor are capacitively coupled to the erase node via a tunnel dielectric.

Claims

1. A two-transistor, zero-power, electrically-alterable non-volatile latch element comprising:

an input node;

an output node;

an erase node;

a P-Channel MOS transistor having a source connected to a source of a first electrical potential, a drain connected to said output node, a control gate connected to said input node, and a floating gate capacitively coupled to said control gate;

an N-Channel MOS transistor having a source connected to a source of a second electrical potential lower than said first electrical potential, a drain connected to said output node, a control gate connected to said input node, and a floating gate capacitively coupled to said control gate and common to said floating gate of said P-Channel MOS transistor;

said floating gates of said P-Channel MOS transistor and said N-Channel MOS transistor capacitively coupled to said erase node via a tunnel dielectric.

2. The two-transistor, zero-power, electrically-alterable non-volatile latch element of claim 1, further including a MOS transistor having a drain, a source, and a gate, said gate connected to said output node.

3. An array of two-transistor, zero-power, electrically-alterable non-volatile latch elements comprising:

a row line for each row in said array;

a column line for each column in said array, each column line forming an intersection with each row line in said array;

a plurality of two-transistor, zero-power, electrically-alterable non-volatile latch elements arranged in array of rows and columns, each of said two-transistor, zero-power, electrically-alterable non-volatile latch elements disposed at one of said intersections and comprising an input node, an output node, an erase node, a P-Channel MOS transistor having a source connected to a source of a first electrical potential, a drain connected to said output node, a control gate connected to said input node, and a floating gate capacitively coupled to said control gate, an N-Channel MOS transistor having a source connected to a source of a second electrical potential lower than said first electrical potential, a drain connected to said output node, a control gate connected to said input node, and a floating gate capacitively coupled to said control gate and common to said floating gate of said P-Channel MOS transistor, said floating gates of said P-Channel MOS transistor and said N-Channel MOS transistor capacitively coupled to said erase node via a tunnel dielectric, and a select transistor, each of said select transistors having, a source, source connected to said input node, a drain connected to the one of said column lines associated with its intersection, and a gate connected to the one of said row lines associated with its intersection;

common erase line connected to the erase node of each of said two-transistor, zero-power, electrically-alterable non-volatile latch element in said array;

circuitry for selectively connecting each of said row lines to a voltage selected from ground and Vpp; and

circuitry for selectively connecting each of said column lines to a voltage selected from ground and Vpp.