×

Two-transistor zero-power electrically-alterable non-volatile latch

  • US 5,587,603 A
  • Filed: 01/06/1995
  • Issued: 12/24/1996
  • Est. Priority Date: 01/06/1995
  • Status: Expired due to Term
First Claim
Patent Images

1. A two-transistor, zero-power, electrically-alterable non-volatile latch element comprising:

  • an input node;

    an output node;

    an erase node;

    a P-Channel MOS transistor having a source connected to a source of a first electrical potential, a drain connected to said output node, a control gate connected to said input node, and a floating gate capacitively coupled to said control gate;

    an N-Channel MOS transistor having a source connected to a source of a second electrical potential lower than said first electrical potential, a drain connected to said output node, a control gate connected to said input node, and a floating gate capacitively coupled to said control gate and common to said floating gate of said P-Channel MOS transistor;

    said floating gates of said P-Channel MOS transistor and said N-Channel MOS transistor capacitively coupled to said erase node via a tunnel dielectric.

View all claims
  • 5 Assignments
Timeline View
Assignment View
    ×
    ×