Redundancy analyzer for automatic memory tester

• US 5,588,115 A
• Filed: 01/29/1993
• Issued: 12/24/1996
• Est. Priority Date: 01/29/1993
• Status: Expired due to Term

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Augarten, Michael H.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/011,003
• Time in Patent Office: 1,425 Days
• Field of Search: 395/575, 395/400, 395/425, 395/700, 395/800, 395/325, 395/183.05, 395/183.18, 371/10.3, 371/21.2, 371/21.1, 371/24, 371/27, 371/29.1, 371/40.1, 371/16.5, 371/22.6, 364/243, 364/243.1, 364/245, 364/245.3, 364/268.3
• US Class Current: 714/29
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

Memory test apparatus including a redundancy analyzer with a catch RAM transfer interface circuit receiving fault information for a plurality of regions of a memory under test simultaneously in parallel and transmitting the information for each region to a respective one of a plurality of region modules that each has a region input circuit, a region fault RAM, and a microprocessor connected to have access to the region fault RAM, the region fault RAMs storing fault addresses identifying the locations of faults in the memory under test.

Claims

1. Memory test apparatus for testing a memory under test (MUT) formed from physical structures which define a plurality of storage locations organized into a plurality of regions, said apparatus comprising:

a) means for testing the plurality of storage locations in the MUT and generating fault signals indicating which of the plurality of storage locations in the MUT is faulty,

b) a plurality of region modules, each said module having an input, and each said region module comprising;

i) a region fault RAM storing data,

ii) analysis means, connected to said region fault RAM, for analyzing the data in the region fault RAM to identify faulty structures within the MUT, and

iii) input means, coupled to the input of the region module and the region fault RAM, for storing information from the input to the region fault RAM, and

c) interface means, having an input connected to the means for testing and a plurality of outputs, each output coupled to a region module, for routing fault signals indicating a faulty location to the input of a region module which is selected based on the region of the MUT which contains the faulty location.

2. The memory test apparatus of claim 1 wherein said interface means includes OR gates to combine fault signals indicating faulty storage locations in more than one region in the MUT.

3. The memory test apparatus of claim 1 wherein said interface means includes multiplexers.

4. The memory test apparatus of claim 1 wherein said interface means includes a transfer clock and the transfer clock is connected to all said region modules.

5. The memory test apparatus of claim 1 wherein the means for testing comprises a catch RAM having data output nodes coupled to the fault signals.

6. The memory test apparatus of claim 1 wherein said means for testing comprises a comparator having an output coupled to the fault signals.

7. The memory test apparatus of claim 1 wherein said input means is a logic array.

8. The memory test apparatus of claim 1 wherein the analysis means in each said region module includes a microprocessor and program RAM connected to the microprocessor.

9. The memory test apparatus of claim 8 further comprising;

a) a host computer; and

b) a data bus interface means for connecting the host computer to all said region modules to access said program RAM and said fault RAM.

10. The memory test apparatus of claim 1 wherein each said input means comprises means for generating MUT fault address data identifying the locations of faults in said MUT, and wherein said region fault RAM is connected to store said MUT fault address data.

11. The memory test apparatus of claim 10 wherein said means for generating fault address data includes an error counter circuit that generates fault RAM addresses for storing said MUT fault address data in said fault RAM by counting errors in said fault information.

12. The memory test apparatus of claim 11 wherein said means for generating fault address data includes a data counter circuit that generates said MUT fault address data stored in said fault RAM by counting transfer clock pulses that are synchronous with said fault information.

13. The memory test apparatus of claim 12 wherein said means for generating fault address data includes an error detector that detects errors in said fault information and enables said error counter circuit to count transfer clock pulses corresponding to errors in said fault information.

14. A memory test apparatus for analyzing fault information for a memory under test (MUT), said apparatus comprising;

a) a computer work station,

b) means, connected to the computer work station and operating in response to commands from the computer work station, for generating fault information from said memory under test,

c) a capture RAM connected to the means for generating fault information,

d) at least one fault RAM connected to said capture RAM,

e) means for transferring data from the capture RAM to the fault RAM, and

f) microprocessor means, connected to have access to said fault RAM, for analyzing said MUT fault.

15. The memory test apparatus of claim 14 wherein said means for transferring data includes an error counter circuit that generates fault RAM addresses for storing said MUT fault address data in said fault RAM by counting errors in said fault information.

16. The memory test apparatus of claim 15 wherein said means for transferring data includes a data counter circuit that generates said MUT fault address data stored in said fault RAM by counting transfer clock pulses that are synchronous with said fault information.

17. The memory test apparatus of claim 16 wherein said means for transferring data includes an error detector that detects errors in said fault information and enables said error counter circuit to count transfer clock pulses corresponding to errors in said fault information.

18. The memory test apparatus of claim 17 wherein said means for transferring data includes a cycle counter circuit that counts said transfer clock pulses and provides a first enable signal to said data counter circuit when the counted transfer clock pulses exceed a start count.

19. The memory test apparatus of claim 18 wherein said first enable signal is discontinued when the counted transfer clock pulses exceed a stop count.

20. The memory test apparatus of claim 19 wherein said cycle counter circuit includes an ignore serial error (ISE) input, and said cycle counter circuit does not output said first enable signal when disabled by said ISE input.

21. The memory test apparatus of claim 18 wherein said cycle counter circuit includes said error detector and provides a second enable signal to said error counter circuit when the counted transfer clock pulses exceed a start count and an error has been detected in said fault information, said error counter circuit counting said transfer clock pulses when enabled by said second enable signal.

22. The memory test apparatus of claim 21 wherein said second enable signal is discontinued when the counted transfer clock pulses exceed a stop count.

23. The memory test apparatus of claim 17 wherein said fault input means includes RAM write logic that outputs a chip enable signal to said fault RAM, said chip enable signal enabling said fault RAM to store a new MUT fault address datum output by said data counter circuit at a new fault RAM address output by said error counter subsequent to both said counter circuits being incremented by a transfer clock pulse.

24. The memory test apparatus of claim 23 further comprising a first delay circuit that provides a delayed transfer clock pulse to said RAM write logic, said delayed transfer clock pulse causing said chip enable signal to enable said fault RAM to write.

25. The memory test apparatus of claim 24 wherein said RAM write logic causes said chip enable signal to disable said fault RAM prior to counting of a transfer clock pulse by said data counter and said error counter.

26. The memory test apparatus of claim 25 further comprising a second delay circuit that delays transfer clock pulses counted by said data counter circuit and said error counter circuit, and wherein said first delay circuit delays the delayed transfer clock pulses output by said another delay circuit.

27. The memory test apparatus of claim 26 wherein undelayed transfer clock pulses cause said RAM write logic to disable said fault RAM.

28. The memory test apparatus of claim 15 wherein said means for transferring data comprises means for transferring the address of faulty locations in the MUT to the fault RAM.