System and method for a snooping and snarfing cache in a multiprocessor computer system
First Claim
1. An apparatus configured to be inserted into a multiprocessor system having a plurality of data elements and a plurality of processor nodes coupled together by a shared interconnect, the shared interconnect configured to carry a plurality of data elements, the apparatus comprising:
- a processor node;
a cache configured to cache a group of the plurality of data elements for the processor node; and
a snarfing mechanism, coupled to the cache, the snarfing mechanism, when inserted into the multiprocessor system, configured to check the cache to determine if the cache contains a copy of a data element appearing on the shared interconnect, and further programmed to snarf the data element off the shared interconnect if the cache has no copy of the data element.
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Abstract
An improved multiprocessor computer system with an improved snarfing cache is disclosed. The multiprocessor system includes a main memory, I/O interface, and a plurality of processor nodes. Each processor node includes a CPU, and a cache. A shared interconnect couples the main memory, I/O interface, and the plurality of processor nodes. The snarfing cache of each processor node snarfs valid data that appears on the shared interconnect, regardless of whether the cache of the processor node has an invalid copy or no copy of the data. The net effect is that each processor node locally caches additional valid data, resulting in an expected improved cache hit rate, reduced processor latency, and fewer transactions on the shared interconnect.
71 Citations
28 Claims
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1. An apparatus configured to be inserted into a multiprocessor system having a plurality of data elements and a plurality of processor nodes coupled together by a shared interconnect, the shared interconnect configured to carry a plurality of data elements, the apparatus comprising:
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a processor node; a cache configured to cache a group of the plurality of data elements for the processor node; and a snarfing mechanism, coupled to the cache, the snarfing mechanism, when inserted into the multiprocessor system, configured to check the cache to determine if the cache contains a copy of a data element appearing on the shared interconnect, and further programmed to snarf the data element off the shared interconnect if the cache has no copy of the data element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A multiprocessor system having a plurality of data elements and a plurality of processor nodes coupled together by a shared interconnect, the shared interconnect configured to carry a plurality of data elements, each of the processor nodes comprising:
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a cache configured to cache a group of the plurality of data elements for the processor node; and a snarfing mechanism, coupled to the cache, the snarfing mechanism, when inserted into the multiprocessor system, configured to check the cache to determine if the cache contains a copy of a data element appearing on the shared interconnect, and further programmed to snarf the data element off the shared interconnect if the cache has no copy of the data element. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A data caching method for a processor node and cache in a multiprocessor system having a plurality of processor nodes coupled together by a shared interconnect, the shared interconnect configured to carry a plurality of data elements, the method comprising the steps of:
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providing one of the plurality of data elements over the shared interconnect; determining if the cache contains a copy of the data element appearing on the shared interconnect; snarfing the data element off the shared interconnect if the cache has no copy of the data element; and storing the data element snarfed from the shared interconnect in the cache. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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Specification