Microelectromechanical signal processor fabrication

• US 5,589,082 A
• Filed: 06/07/1995
• Issued: 12/31/1996
• Est. Priority Date: 12/11/1992
• Status: Expired due to Term

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Pisano, Albert P., Howe, Roger T., Lin, Liwei, Nguyen, Clark T.
• Primary Examiner(s): POWELL, WILLIAM A
• Application Number:
  US08/480,467
• Time in Patent Office: 573 Days
• Field of Search: 216/2, 216/11, 216/13, 216/20, 216/33, 216/41, 216/67, 156/643.1, 156/650.1, 156/651.1, 156/657.1, 156/659.11, 156/662.1, 333/186
• US Class Current: 216/2
• CPC Class Codes: H03H 9/02275 Comb electrodes
• CPC Class Codes: H03H 9/02377 Symmetric folded-flexure
• CPC Class Codes: H03H 9/46 Filters multiple-port electromechanical filters H03H9/70
• CPC Class Codes: H03H 9/462 Microelectro-mechanical filters

Abstract

A micromechanical filter having planar components, and manufacturable using very large scale integrated circuit microfabrication techniques. The input and output transducers are interdigitated comb electrodes. The mechanical coupling between the input and output transducers includes planar flexures, displacement of the electrodes producing bending of the elements of the flexures. By sealing micromechanical filters in a vacuum and providing on-board circuitry, high signal-to-noise ratios and quality factors are achievable. Construction of a real-time spectrum analyzer using many micromechanical resonators, provides a device with high accuracy and a short sample time.

Claims

1. A method for fabrication of a microelectromechanical signal processor on a substrate, said method comprising the steps of:

(a) fabricating a first patterned layer on said substrate;

(b) fabricating a second patterned layer having an opening for anchoring a third patterned layer;

(c) fabricating said third patterned layer;

(d) fabricating a fourth patterned layer having an opening for anchoring a fifth patterned layer;

(e) fabricating said fifth patterned layer; and

(f) etching said fourth layer and said second layer.

2. The method of claim 1 wherein step (b) further includes providing dimples in said second layer.

3. The method of claim 1 wherein said first, third and fifth layers include polycrystalline silicon.

4. The method of claim 1 wherein said second and fourth layers include phosphosilicate glass.

5. The method of claim 1 further including the steps of:

(g) after step (e) and before step (f) fabricating a structure comprising a sixth patterned layer;

(h) after step (g) and before step (f) fabricating a seventh patterned layer having etch holes;

(i) after step (f) fabricating an eighth layer for sealing said etch holes in said seventh layer; and

wherein said structure is etched in step (f).

6. The method of claim 5 further including the step of drying said substrate using a supercritical CO₂ process after step (f) and before step (i).

7. The method of claim 5 wherein said seventh and eighth layers include low-stress silicon nitride.

8. The method of claim 5 wherein step (i) is carried out at low pressure.