Field emission device with lattice vacancy post-supported gate

• US 5,589,728 A
• Filed: 05/30/1995
• Issued: 12/31/1996
• Est. Priority Date: 05/30/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Taylor, Robert, Shen, Chi-Cheong, Levine, Jules D.
• Primary Examiner(s): O'Shea, Sandra L.
• Assistant Examiner(s): HAYNES, MACK NELSON
• Application Number:
  US08/453,043
• Time in Patent Office: 581 Days
• Field of Search: 313/306, 313/309, 313/310, 313/336, 313/351, 313/495, 313/496, 313/497, 345/75, 345/74
• US Class Current: 313/336
• CPC Class Codes: H01J 3/022 with microengineered cathode, e.g. Spindt-type
• CPC Class Codes: H01J 9/025 of field emission cathodes

Abstract

An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by a dielectric insulating spacer (125) from a cathode electrode including a conductive mesh (18). Arrays (12) of microtips (14) are located in mesh spacings (16), within apertures (26) formed in clusters (23) in extraction electrode (22). Microtips (14) are deposited through the apertures (26). Apertures (26) are arranged in regular, periodic arrays (23, 23'"'"', 123, 123'"'"') defining lattices having occupied apertured positions and internal unapertured vacancy positions (150, 150'"'"'). The insulating spacer (125) is etched to undercut electrode (22) to connect apertured lattice positions, forming a common cavity (141) for microtips (14) within each mesh spacing (16), and leaving central posts (143) at the unapertured vacancies (150, 150'"'"'). The etch-out reduces the dielectric constant factor of gate-to-cathode capacitance in the finished structure. Placing posts at vacancy positions enables gate support over the cavity without sacrificing high microtip density.

Claims

1. An electron emitter plate comprising:

a substrate;

a first layer of conductive material deposited on said substrate;

a layer of insulating material deposited on said substrate over said first layer of conductive material;

a second layer of conductive material deposited on said substrate over said layer of insulating material;

said second layer of conductive material having a plurality of apertures;

said apertures being arranged in a regular, periodic array defining a lattice having at least one internal vacancy;

a conductive microtip formed in each aperture in electrical communication with said first layer of conductive material;

said insulating layer being formed with a cavity connecting said apertures and commonly containing said microtips;

said insulating layer supporting said second layer of conductive material above said first layer of conductive material peripherally of said cavity; and

said insulating layer forming a post under each lattice vacancy, said post supporting said second layer of conductive material above said first layer of conductive material centrally of said cavity.

2. The electron emitter plate of claim 1, wherein said apertures are arranged in a rectangular matrix array.

3. The electron emitter plate of claim 1, wherein said apertures are arranged in a staggered array, so that lines joining centers of adjacent apertures and vacancies define triangular areas on said second layer of conductive material.

4. The electron emitter plate of claim 3, wherein said triangular areas are equilateral triangular areas.

5. The electron emitter plate of claim 1, wherein said at least one internal vacancy is a vacancy located at the center of said lattice, and said insulating layer forms a central post under said center vacancy.

11. The electron emitter plate of claim 1, wherein said first layer of conductive material is patterned in stripes;

and said second layer of conductive material is patterned in cross-stripes;

said stripes and cross-stripes intersecting at pixel-defining locations.

12. An image display device comprising the electron emitter plate of claim 1, and further comprising an anode plate spaced from said emitter plate and including an anode substrate, another layer of conductive material deposited on said anode substrate, and cathodoluminescent material in electrical communication with said another layer of conductive material.

6. An electron emitter plate comprising:

a substrate;

a first layer of conductive material deposited on said substrate;

said first layer of conductive material being patterned in a mesh structure defining a plurality of mesh spacings;

a layer of insulating material deposited on said substrate over said first layer of conductive material and said mesh spacings;

a second layer of conductive material deposited on said substrate over said layer of insulating material;

said second layer of conductive material having a cluster of apertures located within each mesh spacing;

the apertures of each cluster being arranged in a regular, periodic array defining a lattice having at least one internal vacancy;

a conductive microtip formed in each aperture in electrical communication with said first layer of conductive material;

said insulating layer being formed with a cavity located within each mesh spacing, each cavity connecting the apertures of one of said clusters and commonly containing the microtips associated with that cluster;

said insulating layer supporting said second layer of conductive material above said first layer of conductive material peripherally of each cavity; and

said insulating layer forming a post under each lattice vacancy, said post supporting said second layer of conductive material above said first layer of conductive material centrally of each cavity.

7. The electron emitter plate of claim 6, wherein said second layer of conductive material is patterned to form pads respectively located centrally within said mesh spacings, and bridging strips electrically connecting said pads to neighboring pads;

said aperture clusters being respectively located on said pads.

8. The electron emitter plate of claim 7, wherein said insulating layer supports each pad marginally, peripherally of each cavity, and supports each pad centrally, centrally of each cavity.

9. The electron emitter plate of claim 8, wherein said mesh spacings and pads are rectangular.

10. The electron emitter plate of claim 9, wherein said at least one internal vacancy is a vacancy located at the center of said lattice, and said insulating layer forms a central post under said center vacancy.