Method for final testing of semiconductor devices

• US 5,589,765 A
• Filed: 01/04/1995
• Issued: 12/31/1996
• Est. Priority Date: 01/04/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Marrero, Deogracias D., Ohmart, Dale V., Mirizzi, Douglas J., Benitez, Willie B. III
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): BOWSER, BARRY
• Application Number:
  US08/368,683
• Time in Patent Office: 727 Days
• Field of Search: 324/158.1, 324/26, 324/56, 324/73.1, 324/72.5, 364/483
• US Class Current: 324/757.01
• CPC Class Codes: G01R 31/01 Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: G01R 31/319 Tester hardware, i.e. output processing circuits
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A method is provided for more efficiently and inexpensively testing semiconductor devices by an automated process of monitoring the performance of the test equipment and certifying that it is working properly, both before and after the actual tests of the devices are conducted. If the automated process can certify that the test equipment was working properly, prior and subsequent to the actual tests of the devices, then it can be assumed that the actual tests were performed correctly and the results are valid. Those devices that "passed" the actual tests are then ready for the next step in the fabrication process, or typically ready to be shipped to the customer. If the test equipment'"'"'s performance degrades significantly during the actual tests, then the results of the actual tests are considered invalid. Consequently, the test equipment can be repaired or recalibrated and all of the devices retested.

Claims

1. A method for final testing a lot consisting of a predetermined plurality of semiconductor devices, comprising the steps of:

testing operation of a test system relative to a predetermined set of test system performance characteristics;

if said test system fails to operate in accordance with said predetermined set of test system performance characteristics, repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics;

certifying that said test system is operating in accordance with said predetermined set of test system performance criteria;

testing a plurality of semiconductor device performance characteristics of each of said lot of semiconductor devices with said test system, said testing resulting in passing semiconductor devices operating in accordance with said plurality of semiconductor device performance characteristics and failing semiconductor devices not operating in accordance with said plurality of semiconductor device performance characteristics;

subsequent to said testing of said lot of semiconductor devices, testing operation of said test system relative to said predetermined set of test system performance characteristics;

if said test system fails to operate in accordance with said predetermined set of test system performance criteria subsequent to said testing of said lot of semiconductor devices

repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics,

following repair of said test system restarting testing each of said lot of semiconductor devices and subsequent to said restart of testing of said lot of semiconductor devices retesting operation of said test system;

if said test system operates in accordance with said predetermined set of test system performance criteria subsequent to said testing of said lot of semiconductor devices, recertifying that said test system is operating in accordance with said predetermined set of test system performance criteria; and

packing and shipping said passing semiconductor devices.

2. The method according to claim 1, wherein said certifying step further comprises comparing a plurality of test system performance characteristics with a predetermined set of statistical rules.

3. The method according to claim 1, wherein said certifying step further comprises comparing a plurality of test system performance characteristics with a plurality of modified WECO rules.

4. The method according to claim 1, wherein at least one of said predetermined set of performance criteria is certified during said step of testing.

9. The method according to claim 1, further comprising the steps of:

following testing of one half of said lot of semiconductor devices, testing operation of said test system relative to a at least one of said predetermined set of test system performance characteristics;

if said test system fails to operate in accordance with said at least one of said predetermined set of test system performance criteria

repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics,

following repair of said test system restarting testing each of said lot of semiconductor devices and subsequent to said retesting of said lot of semiconductor devices retesting operation of said test system; and

if said test system operates in accordance with said at least one of said predetermined set of test system performance criteria, continuing with testing of a second half of said lot of semiconductor devices.

10. The method of claim 9, wherein:

said at least one of said predetermined set of test system performance characteristics includes verification that said test system has a device temperature setting equal to a predetermined temperature.

11. The method of claim 9, wherein:

said at least one of said predetermined set of test system performance characteristics includes verification that said test system has device under-temperature and device over-temperature settings within a predetermined range of respective predetermined temperatures.

12. The method of claim 1, wherein:

said tester system conveys passing semiconductor devices into a pass bin;

said tester system maintains a count of passing semiconductor devices; and

said test system periodically requests verification that said test system count of passing semiconductor devices equals a number of semiconductor devices in said pass bin;

if said test system count of passing semiconductor devices fails to equal said number of semiconductor devices in said pass bin

repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics,

following repair of said test system restarting testing each of said lot of semiconductor devices and subsequent to said retesting of said lot of semiconductor devices retesting operation of said test system; and

if said test system count of passing semiconductor devices equals said number of semiconductor devices in said pass bin, continuing with testing of said lot of semiconductor devices.

13. The method of claim 1, wherein:

said tester system maintains a count of passing semiconductor devices;

said testing operation of said test system subsequent to said testing of said lot of semiconductor devices includes comparing a ratio of said count of passing semiconductor devices to a number of semiconductor devices in said lot of semiconductor devices to a predetermined ratio;

if said ratio of said count of passing semiconductor devices to a number of semiconductor devices in said lot of semiconductor devices is less than said predetermined ratio

repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics,

following repair of said test system restarting testing each of said lot of semiconductor devices and subsequent to said retesting of said lot of semiconductor devices retesting operation of said test system; and

if said ratio of said count of passing semiconductor devices to a number of semiconductor devices in said lot of semiconductor devices is less than said predetermined ratio, continuing with other tests in said testing operation of said test system subsequent to said testing of said lot of semiconductor devices.

5. A method for final testing of a lot of a predetermined number of semiconductor integrated circuits, comprising the steps of:

loading said lot of said semiconductor integrated circuits into a semiconductor device test handler;

measuring a plurality of tester performance characteristics of a semiconductor device tester coupled to said test handler;

measuring a plurality of test handler performance characteristics of said test handler;

comparing said plurality of tester performance characteristics to a predetermined set of tester criteria and said plurality of test handler performance characteristics to a predetermined set of test handler criteria;

if either said tester fails to operate in accordance with said predetermined set of tester criteria or said test handler fails to perform in accordance with said teat handler criteria, repairing said tester and said test handler and remeasuring said tester performance characteristic and said test handler performance characteristic until both said tester operates in accordance with said predetermined set of tester criteria and said test handler operates in accordance with said predetermined set of test handler criteria;

if both said tester operates in accordance with said predetermined set of tester criteria and said test handler operates in accordance with said predetermined set of teat handler criteria, measuring a plurality of semiconductor integrated circuit performance characteristics of each of said lot of said semiconductor integrated circuits with said tester;

sorting each of said lot of said semiconductor integrated circuits at an output of said test handler into passing and failing groups in accordance with said measured plurality of semiconductor integrated circuit performance characteristics;

remeasuring said plurality of tester performance characteristics subsequent to said measuring said plurality of semiconductor performance characteristics of said lot of semiconductor integrated circuits;

remeasuring said plurality of test handler performance characteristics subsequent to said measuring said plurality of semiconductor performance characteristics of said lot of semiconductor integrated circuits;

recomparing said remeasured plurality of tester performance characteristics to said predetermined set of tester criteria and said remeasured plurality of test handler performance characteristics to said predetermined set of test handler criteria;

if either said tester fails to operate in accordance with said predetermined set of tester criteria on remeasurement or said test handler fails to perform in accordance with said teat handler criteria on remeasurement, repairing said tester and said test handler and remeasuring said tester performance characteristic and said test handler performance characteristic until both said tester operates in accordance with said predetermined set of tester criteria and said test handler operates in accordance with said predetermined set of test handler criteria, and thereafter remeasuring said plurality of semiconductor integrated circuit performance characteristics of each of said lot of said semiconductor integrated circuits with said tester;

if both said tester operates in accordance with said predetermined set of tester criteria on remeasurement and said test handler operates in accordance with said predetermined set of teat handler criteria on remeasurement, then packing and shipping said semiconductor integrated circuits in said passing group.

6. The method according to claim 5, wherein said first and second predetermined set of criteria further comprise a plurality of statistical rules.

7. The method according to claim 6, further comprising the steps of:

repairing at least one of said handler and said tester if at least one of said measured second and third plurality of performance characteristics violates at least one of said plurality of statistical rules during the comparing step; and

if said repairing step is performed, unloading said semiconductor integrated circuits from said handler and returning to said loading step.

8. The method according to claim 6, further comprising the steps of:

repairing at least one of said handler and said tester if at least one of said remeasured second and third plurality of performance characteristics violates at least one of said plurality of statistical rules during the recomparing step; and

if said repairing step is performed, unloading said semiconductor integrated circuits from said handler and returning to said loading step.

14. The method according to claim 5, further comprising the steps of:

following measuring said predetermined set of semiconductor integrated circuit performance characteristic of one half of said lot of semiconductor integrated circuits, making an intermediate remeasurement of at least one of said tester relative to at least one of said predetermined set of tester performance characteristics and said test handler relative to at least one of said predetermined set of test handler performance characteristics;

if either said tester fails to operate in accordance with said predetermined set of tester criteria on said intermediate remeasurement or said test handler fails to perform in accordance with said test handler criteria on said intermediate remeasurement, repairing said tester and said test handler and remeasuring said tester performance characteristic and said test handler performance characteristic until both said tester operates in accordance with said predetermined set of tester criteria and said test handler operates in accordance with said predetermined set of test handler criteria, and thereafter remeasuring said plurality of semiconductor integrated circuit performance characteristics of each of said lot of said semiconductor integrated circuits with said tester; and

if both said tester operates in accordance with said predetermined set of tester criteria on said intermediate remeasurement and said test handler operates in accordance with said predetermined set of teat handler criteria on said intermediate remeasurement, continuing with testing of a second half of said lot of semiconductor integrated circuits.

15. The method of claim 14, wherein:

said at least one of said predetermined set of test handler performance characteristics includes verification that said test handler has a device temperature setting equal to a predetermined temperature.

16. The method of claim 14, wherein:

said at least one of said predetermined set of test handler performance characteristics includes verification that said test handler has device under-temperature and device over-temperature settings within a predetermined range of respective predetermined temperatures.

17. The method of claim 5, wherein:

said tester maintains a count of passing semiconductor integrated circuits; and

said tester periodically requests verification that said tester count of passing semiconductor devices equals a number of semiconductor devices in said passing group;

if said tester count of passing semiconductor devices fails to equal said number of semiconductor devices in said passing group, repairing said tester and said test handler and remeasuring said tester performance characteristic and said test handler performance characteristic until both said tester operates in accordance with said predetermined set of tester criteria and said test handler operates in accordance with said predetermined set of test handler criteria, and thereafter remeasuring said plurality of semiconductor integrated circuit performance characteristics of each of said lot of said semiconductor integrated circuits with said tester; and

if said tester count of passing semiconductor integrated circuits equals said number of semiconductor integrated circuits in said passing group, continuing with testing of said lot of semiconductor integrated circuits.

18. The method of claim 5, wherein:

said testing operation of said tester subsequent to said testing of said lot of semiconductor integrated circuits includes comparing a ratio of said count of passing semiconductor integrated circuits to a number of semiconductor integrated circuits in said lot of semiconductor integrated circuits to a predetermined ratio;

if said ratio of said count of passing semiconductor integrated circuits to said number of semiconductor integrated circuits in said lot of semiconductor integrated circuits is less than said predetermined ratio, repairing said tester and said test handler and remeasuring said tester performance characteristic and said test handler performance characteristic until both said tester operates in accordance with said predetermined set of tester criteria and said test handler operates in accordance with said predetermined set of test handler criteria, and thereafter remeasuring said plurality of semiconductor integrated circuit performance characteristics of each of said lot of said semiconductor integrated circuits with said tester; and

if said ratio of said count of passing semiconductor integrated circuits to a number of semiconductor integrated circuits in said lot of semiconductor devices is less than said predetermined ratio, continuing with other tests in said testing operation of said test system subsequent to said testing of said lot of semiconductor devices.