Asynchronous bidirectional application program processes interface for a distributed heterogeneous multiprocessor system

• US 5,590,281 A
• Filed: 10/28/1991
• Issued: 12/31/1996
• Est. Priority Date: 10/28/1991
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: The United States of America As Represented By The Secretary of Agriculture
• Inventors: Stevens, Bruce W.
• Primary Examiner(s): Kriess, Kevin A.
• Assistant Examiner(s): Richey, Michael T.
• Application Number:
  US07/783,661
• Time in Patent Office: 1,891 Days
• Field of Search: 395/200, 395/32 S, 395/650, 395/700, 395/200.01, 395/200.02, 395/200.03, 395/200.2, 364/228.9, 364/230, 364/DIG 1
• US Class Current: 709/227
• CPC Class Codes: G06F 9/54 Interprogram communication

Abstract

A network interface resident on one processor enables heterogenous processors interconnected by a common network to exchange control and data information via virtual circuits created and maintained by the network interface between sockets defined at the communicating processors. Different kinds of messages are discriminated and their length is determined to enable the same network virtual circuit to mulitplex data and control information in a manner that is message specific and conserves network resources. Data conversion is implemented to enable heterogeneous processors to communicate over the network virtual circuit. Asynchronous, bidirectional communication is provided by the network interface for tightly-coupled, moderately-coupled, and loosely-coupled hardware architecture conformance types.

Claims

1. For use in a multiprocessing system in which plural and heterogeneous processors perform distributed processing, a subsystem for interfacing component processes of application programs resident in different ones of the plural heterogeneous processors, which subsystem for interfacing asynchronously and bidirectionally enables processing in one and another of at least two heterogeneous processors of the plurality as though the distributed processing was performed under run control of a unitary, undistributed application program, said heterogeneous one and another processors differing by having at least one difference characteristic from among (A) plural, predetermined data representation format characteristics of the plural processors and (B) plural, predetermined different processor architecture characteristics dependent ways of using component processes of an application program, said plural processors being interconnected for multiprocessing by an interprocessor communication subsystem in which signals are borne by a hardware interconnection means, said subsystem for interfacing application program processes comprising:

cross-processor-tasking-of-application-program-components-layer-means residing in the application program level of software hierarchy coupled to a selected processor, which cross-processor-tasking-layer-means is operative to enable one task asynchronous to one component process run by one processor of one heterogeneous kind to use another component task asynchronous to another process run by another processor of another heterogeneous kind in such a way that the fact that the another task is being run by the another processor is transparent to the using processor as if the distributed processing is being performed under run control of a unitary, undistributed application program;

presentation-layer-means residing in the application program level of software hierarchy which is cooperative with the cross-process-tasking-of-application-program-components-layer-means for converting data from the data representation format characteristic of the one processor whose component process is to use the another component process to another data representation format characteristic corresponding to the another processor whose component process is being run thereby and for determining which of plural, predetermined ways the used component process is to be used;

connections-and-task-transport-layer-means in part residing in the application program level of software hierarchy and in part facilitated by the hardware interconnection means of the interprocessor communications subsystem, which connections-and-task-transport-layer-means is cooperative with both the cross-processor-tasking-of-application-program-components-layer-means and the presentation-layer-means for providing a network virtual circuit between sockets defined between the processes borne by the distributed processors and for providing sending and receiving tasks along the network virtual circuit between the sockets of the several processes thereof thereby facilitating execution of the component processor application programs resident in different and heterogeneous processors as though a unitary, undistributed application program were being executed, the hardware interconnection means providing the communication path facilitating unification of execution of the component processes in the separately resident application programs; and

data-and-usage-determined-information-transport-layer-means resident in the application program level of software hierarchy cooperative with the connections-and-task-transport-layer-means for providing data reads and data writes of data representation-format-converted and usage-determined information along the network virtual circuit by the sending and receiving tasks between the sockets of the network virtual circuit.

2. The subsystem for interfacing component processes of application programs in accordance with claim 1, wherein said interprocessor communication subsystem is of the tightly-coupled distributed multiprocessor predetermined architecture conformance type;

and

said hardware interconnection means is a set of bus conductors interconnecting the plural processors with a globally shared memory.

3. The subsystem for interfacing component processes of application programs in accordance with claim 1, wherein said interprocessor communication subsystem is of the loosely-coupled distributed multiprocessor predetermined architecture conformance type;

and

said interprocessor communication subsystem is of the type employing a communication protocol which facilitates both data sharing and synchronization actions.

4. The subsystem for interfacing component processes of application programs in accordance with claim 1, wherein said interprocessor communications subsystem is of the loosely coupled distributed multiprocessor predetermined architecture conformance type;

and

said interprocessor communication subsystem comprises an area network including a signal transmission line and having a store-and-forward information transfer mechanism.

5. The subsystem for interfacing component processes application programs in accordance with claim 1, wherein said cross-processor-tasking-of-application-components-layer-means, which enables one task of one processor to use another task asynchronous to another process of another processor by means of a remote procedure call.

6. The subsystem for interfacing component processes of application programs in accordance with claim 1, wherein that particular function of the presentation-layer-means consisting of determining which one of said plural predetermined ways of using component processes of an application program is to be used, is performed by an included means for representing information to be transferred between processors in in response to both functional-message-kind and message-length such that particular functional-message-kinds and message-lengths enable the used process to be used in one of said predetermined ways along the same network virtual circuit.

7. The subsystem for interfacing component processes of application programs in accordance with claim 6, wherein said included means for representing information to be transferred between processors which represents said functional-message-kinds and said message-lengths is a single Ada computer language instruction of the Ada protocol discriminator type which will return the correct length of the variant component type, whereby the entire length of message to be sent may be determined as the length of the discriminator itself plus the returned length attribute.

8. The subsystem for interfacing component processes of application programs in accordance with of claim 1, wherein said connections-and-task-transport-layer-means providing said network virtual circuit between said sockets includes means for defining an input message queue at each of the processes borne by the processors at corresponding sockets.

9. The subsystem for interfacing component processes of programs in accordance with claim 1, wherein said connections-and-task-transport-layer-means providing said network virtual circuit between sockets further includes means for returning a new socket in response to receipt thereby of a request to use the component process that resides at the corresponding socket.

10. The subsystem for interfacing component processes of application programs in accordance with claim 1, wherein said sending and receiving tasks of said data-and-usage-determined-information-transport-layer means are asynchronous to the processes in which they are embedded.

11. The subsystem for interfacing components processes of application programs in accordance with claim 1, wherein the heterogeneous plural, predetermined data representation formal characteristics include one and another different numerical data representation formats respectively employing opposite byte orders.

12. The subsystem for interfacing component processes of application programs in accordance with claim 1 wherein said ways of using a component process of an application program of said heterogeneous one and the other processors differ at least in the processors'"'"' employment of different characteristic instruction sets in their execution of computer programs;

and

said presentation-layer-means determines the way of use of a used component process on the basis of the characteristic instruction set of the one processor whose component process is to use the other process relative to the characteristic instruction set of the other processor whose component process is being used.

13. The subsystem for interfacing component processes application programs in accordance with claim 3, wherein the communication conduit of a predetermined characteristic type is an area network loop employing the Transmission Control/Interest Protocol (TCP/IP) protocol for stream-oriented communication along signal pipes.

14. The subsystem for interfacing component processes of application programs in accordance with claim 4, wherein the communication conduit of a predetermined type is an area network loop employing the Transmission Control/Interest Protocol (TCP/IP) protocol for stream-oriented communication along signal pipes.