Network station with multiple network addresses

• US 5,590,285 A
• Filed: 08/09/1995
• Issued: 12/31/1996
• Est. Priority Date: 07/28/1993
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Strohl, Niles E., Hart, John H., Krause, Jeffrey, Russell, Steven P., Seaman, Michael J.
• Primary Examiner(s): Shah, Alpesh M.
• Application Number:
  US08/513,167
• Time in Patent Office: 510 Days
• Field of Search: 395/800, 395/841, 395/827, 395/200.20, 395/200.17, 395/200.16, 395/200.15, 380/33, 380/37, 371/8.2, 371/11.2, 371/67.1, 371/68.1, 371/68.2, 370/54, 370/60, 370/60.1, 370/80, 370/85.7, 370/85.13, 370/92, 370/94.1, 370/95.1, 340/825.03, 340/825.07, 340/826
• US Class Current: 709/218
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory. The plurality of data channels served by the media access control device may reside on a single physical interface, or in independent physical interfaces as suits the needs of a particular design. A high performance design would include independent buffering and queuing structures for each of the data channels. An alternative design may include shared buffering and queuing structures for a plurality of functional modules in the connected computer which have independent side network addresses.

Claims

1. A network interface control apparatus for connection of a data processing system including a plurality of processing modules to a network transmission medium in a network, the network having a physical layer and a data link layer comprising:

a connector to transport data to and from the network transmission medium; and

a medium access control device in the data link layer, coupled to the connector, to receive and transmit frames of data through the connector, the medium access control device including,

a plurality of data channels to communicate between the network transmission medium through the connector and respective processing modules in the data processing system, each channel in the plurality of data channels having an assigned data link layer address,

memory to store the assigned data link layer addresses for the plurality of data channels, and

address filtering logic, coupled to the plurality of data channels and the memory, which passes and blocks frames received through the connector in response to the assigned data link layer addresses on the corresponding data channels in the plurality of data channels;

a media arbitration circuit coupled between the connector and the medium access control device, which supplies to the address filtering logic frames of data which are received through the connector from the network transmission medium, and receives from the plurality of data channels, frames of data which are to be transmitted to the network transmission medium from the plurality of data channels.

2. In the apparatus of claim 1, wherein the memory further stores a plurality of additional data link layer addresses in addition to the assigned data link layer addresses for at least a particular data channel in the plurality of data channels, and the address filtering logic includes circuits which pass and block frames received through the connector on the particular data channel in response to the plurality of additional data link layer addresses and the assigned data link layer address.

3. In the apparatus of claim 2, wherein the frames of data include source and destination addresses, and the circuits responsive to the plurality of additional data link layer addresses include logic for blocking a particular frame on the particular data channel when the plurality of additional data link layer addresses includes the source and destination addresses of the particular frame.

4. The apparatus of claim 1, further including a first physical data path connected to the address filtering logic to conduct transmitted and received data in a first data channel in the plurality of data channels and a second physical data path connected to the address filtering logic to conduct transmitted and received data in a second data channel in the plurality of data channels.

5. The apparatus of claim 1, further including a physical data path to conduct transmitted and received frames of data in at least two of the plurality of data channels.

6. The apparatus of claim 1, wherein the media arbitration circuit includes a local collision detection circuit which signals collisions between frames of data to be transmitted to the network transmission medium from the plurality of data channels to the connector.

7. A network interface control apparatus for connection of a computer to a network transmission medium, comprising:

a physical layer device to transport data frames to and from the network transmission medium;

a data link layer device, coupled to the physical layer device, including a plurality of virtual data link layer modules having respective assigned data link layer addresses, and including,

a corresponding plurality of data channels between the physical layer device and respective higher protocol layer modules in the computer,

memory to store assigned network addresses for the plurality of virtual data link layer modules, and

address filtering logic, coupled to the physical layer device, the plurality data channels and the memory, which passes and blocks data frames received from the physical layer device for the plurality of virtual data link layer modules in response to the assigned network addresses for communication with the respective higher protocol layer modules through the plurality of data channels;

a media arbitration circuit coupled to the plurality of virtual data link layer modules, which supplies to the address filtering logic data frames which are received through the physical layer device from the network transmission medium, and receives from the plurality of virtual data link layer modules, data frames which are to be transmitted to the network transmission medium from the plurality of virtual data link layer modules.

8. The apparatus of claim 7, wherein the physical layer device includes:

a circuit which merges the plurality of data channels into a single data path for connection to the network transmission medium.

9. The apparatus of claim 7, wherein the media arbitration circuit includes a local collision detection circuit which signals collisions between data frames to be transmitted to the network transmission medium from the plurality of virtual data link layer modules.

10. The apparatus of claim 7, wherein the memory further stores a plurality of additional network addresses in addition to the assigned network addresses, and the address filtering logic includes circuits responsive to the plurality of additional network addresses.

11. The apparatus of claim 10, wherein the data frames include source and destination addresses, and the circuits responsive to the plurality of additional network addresses include logic for blocking a particular data frame on at least one of the plurality of data channels when the plurality of additional network addresses includes the source and destination addresses of the particular data frame.