Digital signal processing system for limiting a result to be predetermined bit count

• US 5,590,291 A
• Filed: 01/04/1993
• Issued: 12/31/1996
• Est. Priority Date: 02/27/1989
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Murakami, Tokumichi, Ohira, Hideo
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US08/000,562
• Time in Patent Office: 1,457 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/375, 395/800, 395/275
• US Class Current: 712/225
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/30 using hierarchical techniques, e.g. scalability H04N19/63 takes precedence
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/51 Motion estimation or motion compensation
• CPC Class Codes: H04N 19/533 Motion estimation using multistep search, e.g. 2D-log search or one-at-a-time search [OTS]
• CPC Class Codes: H04N 19/577 Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
• CPC Class Codes: H04N 19/587 involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence

Abstract

A video codec (coder-decoder) system inputs consecutively admitted frames of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by internal coding circuits. This averages the numbers of significant pixels in the sub-sampled video data to be processed. The coded video data is composed so as to comply with specifications of the receiving equipment. Upon transmission, the data is again sub-sampled depending on the number of coding circuits on the receiving side. Each block of the sub-sampled data is given a header for consecutive transmission. This allows for a certain period of time between pieces of data that arrive at the receiving side, thereby eliminating time differences in receiving and coding.

Claims

1. A digital signal processing system, comprising:

an instruction memory for storing microinstructions;

an instruction execution control circuit for fetching and decoding said microinstructions from said instruction memory, each of said microinstructions including a data operation instruction and a bit limiting instruction designating a significant bit count;

a data memory for storing data;

a data operation circuit for performing an operation on data from said data memory, said operation being designated by a decoded microinstruction from said instruction execution control circuit; and

a limiting circuit for inputting a result of said operation performed by said data operation circuit, inputting a bit limiting instruction from said instruction execution control unit, physically limiting the number of bits of said result to any integer m designated by the bit limiting instruction of said decoded microinstruction, and outputting the limited result to an output bus with a width of n bits, where m<

n.